[libre-riscv-dev] daily kan-ban update 19jul2020

[libre-riscv-dev] daily kan-ban update 19jul2020

[Luke Kenneth Casson Leighton]

yesterday:

* got alu FSM working example with a CompUnit "manager"

today:

* walked through some examples using cxxsim and encountered some bugs,
under investigation.
* talked with florent from enjoy-digital, he is going to add libre-soc
test_issuer to litex upstream for us.

once compiling test_issuer to run under verilator is possible, we *should*
be able to put together a 16550 uart example from fusesoc pretty quickly.

that will allow running of the full microwatt hello_world binary and, as
long as we can get access to the serial console we will have a first
"proper" demo.

from there running the microwatt micropython binary should also be easy.

i have no idea if verilator generates vcd files which would allow debugging
if there are issues (instructions missing for example)

l.



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Re: [libre-riscv-dev] daily kan-ban update 19jul2020

[Yehowshua]

> i have no idea if verilator generates vcd files which would allow debugging
> if there are issues (instructions missing for example)

Verilator does generate VCDs…
LiteX abstracts that away for you, however,
I will say that its a pretty painful process
to run through LiteX generated VCds.

They are flattened as oMigen outputs flat verilog.

Yehowshua
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Re: [libre-riscv-dev] daily kan-ban update 19jul2020

[Luke Kenneth Casson Leighton]

On Sunday, July 19, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:

> > i have no idea if verilator generates vcd files which would allow
> debugging
> > if there are issues (instructions missing for example)
>
> Verilator does generate VCDs…
> LiteX abstracts that away for you, however,
> I will say that its a pretty painful process
> to run through LiteX generated VCds.
>
> They are flattened as oMigen outputs flat verilog


niice.

in our case that's 17,000 flattened signals.

l.



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Re: [libre-riscv-dev] daily kan-ban update 19jul2020

[Yehowshua]

> 
> in our case that's 17,000 flattened signals.


Well, oMigen won’t flatten out verilog black boxes, but it
will flatten out the dram controller for example.

Which hopefully you don’t need to debug…

Verilator retains the hierarchy of whatever it consumes.
SO you’ll get a hierarchical CPU and flat peripherals.


Yehowshua
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Re: [libre-riscv-dev] daily kan-ban update 19jul2020

[Luke Kenneth Casson Leighton]

On Sunday, July 19, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:

> >
> > in our case that's 17,000 flattened signals.
>
> Verilator retains the hierarchy of whatever it consumes.
> SO you’ll get a hierarchical CPU and flat peripherals.


thank goodness for that.

many of the pipeline signals have not been given globally unique names,
meaning there's dozens of duplicate "ready_o" etc. and more.

l.



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