[libre-riscv-dev] 4 Simulators?

[libre-riscv-dev] 4 Simulators?

[Yehowshua]

Hello all - I recently became aware that there a 4 different POWER simulators being worked on?
This is not a good use of resources given that we have access to a bare-metal Talos II.

We can literally run arbitrary instructions on in remotely - this means a simulator should be low priority given that we have an October deadline.

Yehowshua
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] 4 Simulators?

[Michael Nolan]

On 5/7/20 1:33 PM, Yehowshua wrote:
> Hello all - I recently became aware that there a 4 different POWER simulators being worked on?
> This is not a good use of resources given that we have access to a bare-metal Talos II.
>
> We can literally run arbitrary instructions on in remotely - this means a simulator should be low priority given that we have an October deadline.
>
> Yehowshua
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>
I think we do need *a* simulator other than the talos II server. When we 
have the core somewhat working, we will want to run a bunch of tests on 
it, and check those against a reference. While we can use the Talos as a 
reference, running code on it (I assume) will be a somewhat manual 
process, not really amenable to unit testing. If we have a simulator 
though, we can write (or randomly generate) a bunch of unit tests, and 
run them in the simulator and our core and compare the results. So we 
will need *a* simulator.

However, I do agree that we don't need 4.

--Michael


_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] 4 Simulators?

[Luke Kenneth Casson Leighton]

On Thursday, May 7, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:

> Hello all - I recently became aware that there a 4 different POWER
> simulators being worked on?


no. two.

pearpc and the autogenerated one.


This is not a good use of resources given that we have access to a
> bare-metal Talos II.


it really does not help us except when it comes to FP interoperability.

also the qemu pipe is already done and has rhe advantage of acting like a
local POWER machine instead of forcing development to have a permanent hard
internet line.



> We can literally run arbitrary instructions on in remotely - this means a
> simulator should be low priority given that we have an October deadline.


unlike in RISCV we do not have a cycle accurate simulator, we do not have
formal test suites or in fact any asseembly level test suites at all.

therefore as i outlined already a few weeks ago the strategy is to side by
side bootstrap up the following simultaneously and run the EXACT same
instructions on each:

* python simulator
* pearpc simulator pipe (when ready)
* qemu pipe
* bare metal pipe (run on the talos server)
* hardware simulation pipe

i would suggest adding power-gem5 to that list except the build
dependencies are enormous and it leaks 500mb/sec.

by doing side by side comparisons we have a means to bootstrap our way up.

cutting back actually *slows* the project by removing routes to verify the
correctness of our implementation.

also because "doing is learning" the development of the simulators teaches
us what is needed far faster than the HDL could ever be written without
that "experience"

l.



-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] 4 Simulators?

[Yehowshua]

So a total of two simulators - with 
Tobias, Jacob, Michael and Alain working on them?

I’m guessing Tobias, Michael, and Jacob are working on the Python Simulator?

Alain is working on the PearPC simulator?

Yehowshua
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] 4 Simulators?

[Jacob Lifshay]

On Thu, May 7, 2020, 11:30 Yehowshua <yimmanuel3@gatech.edu> wrote:

> So a total of two simulators - with
> Tobias, Jacob, Michael and Alain working on them?
>
> I’m guessing Tobias, Michael, and Jacob are working on the Python
> Simulator?
>

I'm not working on any simulators (except for the experimental
spectre-proof cpu design which is currently on-hold).

Jacob Lifshay
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] 4 Simulators?

[Yehowshua]

> 
> I'm not working on any simulators (except for the experimental
> spectre-proof cpu design which is currently on-hold).
> 
> Jacob Lifshay

Oh - you said LD/ST here.

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006327.html

Yehowshua


_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] 4 Simulators?

[Jacob Lifshay]

On Thu, May 7, 2020, 11:42 Yehowshua <yimmanuel3@gatech.edu> wrote:

>
> >
> > I'm not working on any simulators (except for the experimental
> > spectre-proof cpu design which is currently on-hold).
> >
> > Jacob Lifshay
>
> Oh - you said LD/ST here.
>

:)

Though, I will most likely be writing a reference interpreter for
shader-compiler-ir once I'm back to working on Kazan. Sorta simulator.

Jacob

>
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] 4 Simulators?

[Luke Kenneth Casson Leighton]

On Thu, May 7, 2020 at 7:30 PM Yehowshua <yimmanuel3@gatech.edu> wrote:

> So a total of two simulators - with
> Tobias, Jacob, Michael and Alain working on them?

i noticed that tobias had just committed to the one that had only 1-2
day's work done on it (for michael to do a proof-of-concept and get
qemu and GNU-as up and running).

i moved it to the "unused" subdirectory.

l.

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] 4 Simulators?

[Tobias Platen]

On Thu, 7 May 2020 14:30:07 -0400
Yehowshua <yimmanuel3@gatech.edu> wrote:

> So a total of two simulators - with 
> Tobias, Jacob, Michael and Alain working on them?
> 
> I’m guessing Tobias, Michael, and Jacob are working on the Python Simulator?
Yes I was working on the Python Simulator, and I was also looking into the sourcecode of the Dolphin emulator.
> 
> Alain is working on the PearPC simulator?
> 
> Yehowshua
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev


-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] 4 Simulators?

[Luke Kenneth Casson Leighton]

On Thu, May 7, 2020 at 7:54 PM Tobias Platen
<libre-soc@platen-software.de> wrote:

> Yes I was working on the Python Simulator,

the discussions in the bugtracker center around the auto-generated
one.  i appreciate that there is a lot going on.

> and I was also looking into the sourcecode of the Dolphin emulator.

https://github.com/dolphin-emu/dolphin/blob/master/Source/Core/Core/PowerPC/Interpreter/Interpreter_Integer.cpp

interesting.  this code *might* be a better starting point for SV
augmentation than pearpc, because c++ provides the means to do
operator-overloads (and templates).

btw do not waste time looking at the JIT version.  we absolutely do
not need a JIT interpreted emulator.  we need a *cycle accurate*
emulator.

l.

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev