[libre-riscv-dev] daily kan-ban update 29jul2020

[libre-riscv-dev] daily kan-ban update 29jul2020

[Luke Kenneth Casson Leighton]

task list:

*
https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1

yesterday:

* added unit test for XICS, started debate on lsdev and openpower hdlcores
* sorted silliness in shiftrot proof so Sam can run it

today:

* reviewed div test mods (looks great, jacob)
* received notification on MoU approval, sent out RFP template for
whitequark
* more review of XICS, possible bug found in microwatt xics.vhdl
* sorted out names for CompUnits to make Jean-Paul's life easier
* got word from Florian investigating Litex, sent him an updated verilog
core.

later:

* more on XICS unit tests
* GPU Sync meeting with OpenPOWER Foundation and microwatt developers,
which is one hour later than 2 weeks ago.

l.



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Re: [libre-riscv-dev] daily kan-ban update 29jul2020

[Tobias Platen]

today:

modified LDSTSplitter to conform to PortInterface

On Wed, 29 Jul 2020 17:15:58 +0100
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:


> task list:
> 
> *
> https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1
> 
> yesterday:
> 
> * added unit test for XICS, started debate on lsdev and openpower hdlcores
> * sorted silliness in shiftrot proof so Sam can run it
> 
> today:
> 
> * reviewed div test mods (looks great, jacob)
> * received notification on MoU approval, sent out RFP template for
> whitequark
> * more review of XICS, possible bug found in microwatt xics.vhdl
> * sorted out names for CompUnits to make Jean-Paul's life easier
> * got word from Florian investigating Litex, sent him an updated verilog
> core.
> 
> later:
> 
> * more on XICS unit tests
> * GPU Sync meeting with OpenPOWER Foundation and microwatt developers,
> which is one hour later than 2 weeks ago.
> 
> l.
> 
> 
> 
> -- 
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev


-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 29jul2020

[Cole Poirier]

Yesterday:

* finished coriolis2 workflow scripts and documentation (now includes
  soclayout instructions)
* finished 180nm test ASIC memory layout diagram translation to SVG,
  the hand-drawn version has been replaced with this version on the
  180nm test ASIC wiki page
* got profoundly confused about XICS, LoPAR, PAPR... etc.
  (fortunately Luke figured a temporary solution with microwatt team)

Today:

* start a correspondence with Mitch about getting the original images
  from his book chapters (vector rather than bitmap), and consultation
  on if he would like to use the new SVGs in a future version of the
  book chapters
* documented my completed, current, near future work on my wiki page
* closed several bugs that had been resolved at various points in the
  past few months but hadn't been marked RESOLVED on bugzilla
* start the process of creating a bug report for each diagram that is
  to be converted to SVG
* brainstorming with other project members about recruiting more
  project members
* solicit input from project members on what should be asked about
  the BlackParrot RV664GC 14nm (!!!!) Multicore SoC in my email
  to that project's developers
* Libre-SOC OPF MKII Call

The call will start in just under an hour and a half from now, correct?

Cole

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Re: [libre-riscv-dev] daily kan-ban update 29jul2020

[Luke Kenneth Casson Leighton]

On Wed, Jul 29, 2020 at 9:37 PM Cole Poirier <colepoirier@gmail.com> wrote:

> * Libre-SOC OPF MKII Call
>
> The call will start in just under an hour and a half from now, correct?

correct.

l.

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[libre-riscv-dev] daily kan-ban update 29jul2020

[Luke Kenneth Casson Leighton]

task list:

* https://bugs.libre-soc.org/showdependencytree.cgi?id=383&
maxdepth=1&hide_resolved=1

yesterday:

* sorted yet another LDST Comp Unit bug
* reorganised pipeline tests
* made a start on XICS interrupt controller

today:

* reviewed (and finished?) trap proof.

rest of day:

* other half of XICS then do some unit tests for it

l.



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