[libre-riscv-dev] daily kan-ban update 29jul2020

[libre-riscv-dev] daily kan-ban update 29jul2020

[Luke Kenneth Casson Leighton]

task list:

* https://bugs.libre-soc.org/showdependencytree.cgi?id=383&
maxdepth=1&hide_resolved=1

yesterday:

* sorted yet another LDST Comp Unit bug
* reorganised pipeline tests
* made a start on XICS interrupt controller

today:

* reviewed (and finished?) trap proof.

rest of day:

* other half of XICS then do some unit tests for it

l.



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Re: [libre-riscv-dev] daily kan-ban update 27jul2020

[Cole Poirier]

Heads up Luke today is the 27th, 29th will be this wednesday, we have
our biweekly OpenPower-Libre-SOC meeting

Yesterday:
* spoke to Luke about recruiting more project members and conversion
of bitmap diagrams on wiki into svg
* finished 180nm_single_core_test_asic_memlayout diagram conversion into svg

Today:

* finish conversion of comp_unit_req_rel bitmap to svg
* finish conversion of comp_unit_multi_rw
* documenting how to layout soclayout repo
* creating one bug report under product Documentation per bitmap
diagram for conversion to svg, in order to successfully coordinate
this medium size substantial task. All svg diagram bugs will be
children of the top level bug report "Bug 389 - Review all diagrams on
wiki for translation into SVG" and will be listed in the description
(comment #0) for easy birds-eye-viewing of the progress of this
meta-task <https://bugs.libre-soc.org/show_bug.cgi?id=389#c0>

Cole

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Re: [libre-riscv-dev] daily kan-ban update 27jul2020

[Tobias Platen]

Today:

I was working on l0_cache.py where I got the following error.
ERROR: test_l0_cache_test_bare_wb (__main__.TestL0Cache)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "l0_cache.py", line 361, in test_l0_cache_test_bare_wb
    vl = rtlil.convert(dut, ports=[])# TODOdut.ports())
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/back/rtlil.py", line 1056, in convert
    fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/hdl/dsl.py", line 538, in elaborate
    fragment.add_subfragment(Fragment.get(self._named_submodules[name], platform), name)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/hdl/dsl.py", line 538, in elaborate
    fragment.add_subfragment(Fragment.get(self._named_submodules[name], platform), name)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
  File "/home/isengaara/Hacking/lSOC/TEST/nmigen-soc/nmigen_soc/wishbone/sram.py", line 89, in elaborate
    n_wrport = wrport.en.shape()[0]
TypeError: 'Shape' object is not subscriptable

Am I using the wrong version of nmigen?


On Mon, 27 Jul 2020 11:38:33 -0700
Cole Poirier <colepoirier@gmail.com> wrote:

> Heads up Luke today is the 27th, 29th will be this wednesday, we have
> our biweekly OpenPower-Libre-SOC meeting
> 
> Yesterday:
> * spoke to Luke about recruiting more project members and conversion
> of bitmap diagrams on wiki into svg
> * finished 180nm_single_core_test_asic_memlayout diagram conversion into svg
> 
> Today:
> 
> * finish conversion of comp_unit_req_rel bitmap to svg
> * finish conversion of comp_unit_multi_rw
> * documenting how to layout soclayout repo
> * creating one bug report under product Documentation per bitmap
> diagram for conversion to svg, in order to successfully coordinate
> this medium size substantial task. All svg diagram bugs will be
> children of the top level bug report "Bug 389 - Review all diagrams on
> wiki for translation into SVG" and will be listed in the description
> (comment #0) for easy birds-eye-viewing of the progress of this
> meta-task <https://bugs.libre-soc.org/show_bug.cgi?id=389#c0>
> 
> Cole
> 
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev


-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 27jul2020

[Luke Kenneth Casson Leighton]

On Mon, Jul 27, 2020 at 8:10 PM Tobias Platen
<libre-soc@platen-software.de> wrote:

>   File "/home/isengaara/Hacking/lSOC/TEST/nmigen-soc/nmigen_soc/wishbone/sram.py", line 89, in elaborate
>     n_wrport = wrport.en.shape()[0]
> TypeError: 'Shape' object is not subscriptable

git pull on the nmigen-soc repo, i sorted this a couple weeks ago?

l.

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Re: [libre-riscv-dev] daily kan-ban update 27jul2020

[Tobias Platen]

On Mon, 27 Jul 2020 20:46:08 +0100
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

> On Mon, Jul 27, 2020 at 8:10 PM Tobias Platen
> <libre-soc@platen-software.de> wrote:
> 
> >   File "/home/isengaara/Hacking/lSOC/TEST/nmigen-soc/nmigen_soc/wishbone/sram.py", line 89, in elaborate
> >     n_wrport = wrport.en.shape()[0]
> > TypeError: 'Shape' object is not subscriptable
> 
> git pull on the nmigen-soc repo, i sorted this a couple weeks ago?
> 
> l.
> 
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

The https://github.com/nmigen/nmigen-soc repository was last updated was 5 days, 
while the https://git.libre-soc.org/git/nmigen-soc.git was updated 8 days ago.
I assume that I am using the wrong one.
In this case I would have to update the scripts in dev-env-setup too.
https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-dev-repos;h=255692bd91bdcd42b18ebd608787de77a23e01eb;hb=HEAD

-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 27jul2020

[Luke Kenneth Casson Leighton]

On Monday, July 27, 2020, Tobias Platen <libre-soc@platen-software.de>
wrote:

>
> while the https://git.libre-soc.org/git/nmigen-soc.git was
>


nmigen-soc does not contain sram.  i had to add it.

l.



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[libre-riscv-dev] daily kan-ban update 29jul2020

[Luke Kenneth Casson Leighton]

task list:

*
https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1

yesterday:

* added unit test for XICS, started debate on lsdev and openpower hdlcores
* sorted silliness in shiftrot proof so Sam can run it

today:

* reviewed div test mods (looks great, jacob)
* received notification on MoU approval, sent out RFP template for
whitequark
* more review of XICS, possible bug found in microwatt xics.vhdl
* sorted out names for CompUnits to make Jean-Paul's life easier
* got word from Florian investigating Litex, sent him an updated verilog
core.

later:

* more on XICS unit tests
* GPU Sync meeting with OpenPOWER Foundation and microwatt developers,
which is one hour later than 2 weeks ago.

l.



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Re: [libre-riscv-dev] daily kan-ban update 29jul2020

[Tobias Platen]

today:

modified LDSTSplitter to conform to PortInterface

On Wed, 29 Jul 2020 17:15:58 +0100
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:


> task list:
> 
> *
> https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1
> 
> yesterday:
> 
> * added unit test for XICS, started debate on lsdev and openpower hdlcores
> * sorted silliness in shiftrot proof so Sam can run it
> 
> today:
> 
> * reviewed div test mods (looks great, jacob)
> * received notification on MoU approval, sent out RFP template for
> whitequark
> * more review of XICS, possible bug found in microwatt xics.vhdl
> * sorted out names for CompUnits to make Jean-Paul's life easier
> * got word from Florian investigating Litex, sent him an updated verilog
> core.
> 
> later:
> 
> * more on XICS unit tests
> * GPU Sync meeting with OpenPOWER Foundation and microwatt developers,
> which is one hour later than 2 weeks ago.
> 
> l.
> 
> 
> 
> -- 
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev


-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 29jul2020

[Cole Poirier]

Yesterday:

* finished coriolis2 workflow scripts and documentation (now includes
  soclayout instructions)
* finished 180nm test ASIC memory layout diagram translation to SVG,
  the hand-drawn version has been replaced with this version on the
  180nm test ASIC wiki page
* got profoundly confused about XICS, LoPAR, PAPR... etc.
  (fortunately Luke figured a temporary solution with microwatt team)

Today:

* start a correspondence with Mitch about getting the original images
  from his book chapters (vector rather than bitmap), and consultation
  on if he would like to use the new SVGs in a future version of the
  book chapters
* documented my completed, current, near future work on my wiki page
* closed several bugs that had been resolved at various points in the
  past few months but hadn't been marked RESOLVED on bugzilla
* start the process of creating a bug report for each diagram that is
  to be converted to SVG
* brainstorming with other project members about recruiting more
  project members
* solicit input from project members on what should be asked about
  the BlackParrot RV664GC 14nm (!!!!) Multicore SoC in my email
  to that project's developers
* Libre-SOC OPF MKII Call

The call will start in just under an hour and a half from now, correct?

Cole

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Re: [libre-riscv-dev] daily kan-ban update 29jul2020

[Luke Kenneth Casson Leighton]

On Wed, Jul 29, 2020 at 9:37 PM Cole Poirier <colepoirier@gmail.com> wrote:

> * Libre-SOC OPF MKII Call
>
> The call will start in just under an hour and a half from now, correct?

correct.

l.

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