From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Status on Our RISCV Implementation
Date: Tue, 24 Mar 2020 20:12:12 +0000
Message-ID: <CAPweEDx2ms2HMjHH6NaCg9-JtW6UNSghrgB-y3Xb9pR6SZJdjw@mail.gmail.com> (raw)
In-Reply-To: <CAC2bXD7DfmUgx_OGODHX4ahH7HmwTd5LE0r_jkaxiF+NTuQzkg@mail.gmail.com>
On Tuesday, March 24, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:
However, it's perfectly possible to have software that catches the illegal
> instruction traps and emulates them, allowing running a RISC-V kernel.
oh. yes. good point. qemu will be doing something like this, i believe?
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Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 11:39 Immanuel, Yehowshua U
2020-03-24 12:07 ` Luke Kenneth Casson Leighton
2020-03-24 13:11 ` Immanuel, Yehowshua U
2020-03-24 13:58 ` Luke Kenneth Casson Leighton
2020-03-24 17:44 ` Jacob Lifshay
2020-03-24 20:12 ` Luke Kenneth Casson Leighton [this message]
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