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From: "Immanuel, Yehowshua U" <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Status on Our RISCV Implementation
Date: Tue, 24 Mar 2020 13:11:27 +0000
Message-ID: <CFEB7F13-0C2F-4299-A5DA-6BB3D00EA101@gatech.edu> (raw)
In-Reply-To: <CAPweEDxmXLMMZPLDpm5RUHM9Bn9Ur35++dmo8QNKzPpxNJ-KDw@mail.gmail.com>

> nope.  not for RISC-V.  userspace only.

So I guess we’d have a POWER kernel…
If a binary tries to call RISCV instructions to set supervisor mode register - how is that handled?

Yehowshua
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Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-24 11:39 Immanuel, Yehowshua U
2020-03-24 12:07 ` Luke Kenneth Casson Leighton
2020-03-24 13:11   ` Immanuel, Yehowshua U [this message]
2020-03-24 13:58     ` Luke Kenneth Casson Leighton
2020-03-24 17:44       ` Jacob Lifshay
2020-03-24 20:12         ` Luke Kenneth Casson Leighton

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