From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Status on Our RISCV Implementation
Date: Tue, 24 Mar 2020 10:44:05 -0700
Message-ID: <CAC2bXD7DfmUgx_OGODHX4ahH7HmwTd5LE0r_jkaxiF+NTuQzkg@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDzdwANkVmqbDV0gPc=EAGkhknMNDW72ypTkoW-zFz8Gow@mail.gmail.com>
On Tue, Mar 24, 2020, 06:59 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
> On Tue, Mar 24, 2020 at 1:11 PM Immanuel, Yehowshua U
> <yimmanuel3@gatech.edu> wrote:
>
> > > nope. not for RISC-V. userspace only.
> >
> > So I guess we’d have a POWER kernel…
>
> correct. and POWER TLBs and MMU.
>
> > If a binary tries to call RISCV instructions to set supervisor mode
> register - how is that handled?
>
> from userspace? fail... just like any other userspace RISC-V program
> is not permitted to set a supervisor mode register on any standard
> RISC-V system.
However, it's perfectly possible to have software that catches the illegal
instruction traps and emulates them, allowing running a RISC-V kernel.
Jacob
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Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 11:39 Immanuel, Yehowshua U
2020-03-24 12:07 ` Luke Kenneth Casson Leighton
2020-03-24 13:11 ` Immanuel, Yehowshua U
2020-03-24 13:58 ` Luke Kenneth Casson Leighton
2020-03-24 17:44 ` Jacob Lifshay [this message]
2020-03-24 20:12 ` Luke Kenneth Casson Leighton
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