From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Status on Our RISCV Implementation
Date: Tue, 24 Mar 2020 12:07:31 +0000
Message-ID: <CAPweEDxmXLMMZPLDpm5RUHM9Bn9Ur35++dmo8QNKzPpxNJ-KDw@mail.gmail.com> (raw)
In-Reply-To: <A6C778B3-04E3-47D4-A28A-B6AC55D4A604@gatech.edu>
On Tue, Mar 24, 2020 at 11:39 AM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:
>
> I’m curious, what is the status of our RISCV implementation.
>
> Do we have:
> 1. A decoder - I’m pretty sure we do
using minerva: it will need updating to RV64GC
> 2. A page table walker
nope. not for RISC-V.
> 3. FPU support
yes.
> 4. Supervisor/Hypervisor mode support?
nope. not for RISC-V. userspace only.
l.
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Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 11:39 Immanuel, Yehowshua U
2020-03-24 12:07 ` Luke Kenneth Casson Leighton [this message]
2020-03-24 13:11 ` Immanuel, Yehowshua U
2020-03-24 13:58 ` Luke Kenneth Casson Leighton
2020-03-24 17:44 ` Jacob Lifshay
2020-03-24 20:12 ` Luke Kenneth Casson Leighton
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