* [libre-riscv-dev] Status on Our RISCV Implementation
@ 2020-03-24 11:39 Immanuel, Yehowshua U
2020-03-24 12:07 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 6+ messages in thread
From: Immanuel, Yehowshua U @ 2020-03-24 11:39 UTC (permalink / raw)
To: Libre-RISCV General Development
I’m curious, what is the status of our RISCV implementation.
Do we have:
1. A decoder - I’m pretty sure we do
2. A page table walker
3. FPU support
4. Supervisor/Hypervisor mode support?
Yehowshua
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [libre-riscv-dev] Status on Our RISCV Implementation
2020-03-24 11:39 [libre-riscv-dev] Status on Our RISCV Implementation Immanuel, Yehowshua U
@ 2020-03-24 12:07 ` Luke Kenneth Casson Leighton
2020-03-24 13:11 ` Immanuel, Yehowshua U
0 siblings, 1 reply; 6+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-03-24 12:07 UTC (permalink / raw)
To: Libre-RISCV General Development
On Tue, Mar 24, 2020 at 11:39 AM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:
>
> I’m curious, what is the status of our RISCV implementation.
>
> Do we have:
> 1. A decoder - I’m pretty sure we do
using minerva: it will need updating to RV64GC
> 2. A page table walker
nope. not for RISC-V.
> 3. FPU support
yes.
> 4. Supervisor/Hypervisor mode support?
nope. not for RISC-V. userspace only.
l.
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* Re: [libre-riscv-dev] Status on Our RISCV Implementation
2020-03-24 12:07 ` Luke Kenneth Casson Leighton
@ 2020-03-24 13:11 ` Immanuel, Yehowshua U
2020-03-24 13:58 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 6+ messages in thread
From: Immanuel, Yehowshua U @ 2020-03-24 13:11 UTC (permalink / raw)
To: Libre-RISCV General Development
> nope. not for RISC-V. userspace only.
So I guess we’d have a POWER kernel…
If a binary tries to call RISCV instructions to set supervisor mode register - how is that handled?
Yehowshua
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* Re: [libre-riscv-dev] Status on Our RISCV Implementation
2020-03-24 13:11 ` Immanuel, Yehowshua U
@ 2020-03-24 13:58 ` Luke Kenneth Casson Leighton
2020-03-24 17:44 ` Jacob Lifshay
0 siblings, 1 reply; 6+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-03-24 13:58 UTC (permalink / raw)
To: Libre-RISCV General Development
On Tue, Mar 24, 2020 at 1:11 PM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:
> > nope. not for RISC-V. userspace only.
>
> So I guess we’d have a POWER kernel…
correct. and POWER TLBs and MMU.
> If a binary tries to call RISCV instructions to set supervisor mode register - how is that handled?
from userspace? fail... just like any other userspace RISC-V program
is not permitted to set a supervisor mode register on any standard
RISC-V system.
there will *be* no supervisor mode RISC-V... therefore implementation
of supervisor mode RISC-V registers is completely unnecessary.
userspace RISC-V is only permitted to set userspace RISC-V CSRs.
l.
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* Re: [libre-riscv-dev] Status on Our RISCV Implementation
2020-03-24 13:58 ` Luke Kenneth Casson Leighton
@ 2020-03-24 17:44 ` Jacob Lifshay
2020-03-24 20:12 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 6+ messages in thread
From: Jacob Lifshay @ 2020-03-24 17:44 UTC (permalink / raw)
To: Libre-RISCV General Development
On Tue, Mar 24, 2020, 06:59 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
> On Tue, Mar 24, 2020 at 1:11 PM Immanuel, Yehowshua U
> <yimmanuel3@gatech.edu> wrote:
>
> > > nope. not for RISC-V. userspace only.
> >
> > So I guess we’d have a POWER kernel…
>
> correct. and POWER TLBs and MMU.
>
> > If a binary tries to call RISCV instructions to set supervisor mode
> register - how is that handled?
>
> from userspace? fail... just like any other userspace RISC-V program
> is not permitted to set a supervisor mode register on any standard
> RISC-V system.
However, it's perfectly possible to have software that catches the illegal
instruction traps and emulates them, allowing running a RISC-V kernel.
Jacob
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2020-03-24 11:39 [libre-riscv-dev] Status on Our RISCV Implementation Immanuel, Yehowshua U
2020-03-24 12:07 ` Luke Kenneth Casson Leighton
2020-03-24 13:11 ` Immanuel, Yehowshua U
2020-03-24 13:58 ` Luke Kenneth Casson Leighton
2020-03-24 17:44 ` Jacob Lifshay
2020-03-24 20:12 ` Luke Kenneth Casson Leighton
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