[libre-riscv-dev] Status on Our RISCV Implementation

[libre-riscv-dev] Status on Our RISCV Implementation

[Immanuel, Yehowshua U]

I’m curious, what is the status of our RISCV implementation.

Do we have:
1. A decoder - I’m pretty sure we do
2. A page table walker
3. FPU support
4. Supervisor/Hypervisor mode support?

Yehowshua
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Re: [libre-riscv-dev] Status on Our RISCV Implementation

[Luke Kenneth Casson Leighton]

On Tue, Mar 24, 2020 at 11:39 AM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:
>
> I’m curious, what is the status of our RISCV implementation.
>
> Do we have:
> 1. A decoder - I’m pretty sure we do

using minerva: it will need updating to RV64GC

> 2. A page table walker

nope.  not for RISC-V.

> 3. FPU support

yes.

> 4. Supervisor/Hypervisor mode support?

nope.  not for RISC-V.  userspace only.

l.

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Re: [libre-riscv-dev] Status on Our RISCV Implementation

[Immanuel, Yehowshua U]

> nope.  not for RISC-V.  userspace only.

So I guess we’d have a POWER kernel…
If a binary tries to call RISCV instructions to set supervisor mode register - how is that handled?

Yehowshua
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Re: [libre-riscv-dev] Status on Our RISCV Implementation

[Luke Kenneth Casson Leighton]

On Tue, Mar 24, 2020 at 1:11 PM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:

> > nope.  not for RISC-V.  userspace only.
>
> So I guess we’d have a POWER kernel…

correct.  and POWER TLBs and MMU.

> If a binary tries to call RISCV instructions to set supervisor mode register - how is that handled?

from userspace? fail... just like any other userspace RISC-V program
is not permitted to set a supervisor mode register on any standard
RISC-V system.

there will *be* no supervisor mode RISC-V... therefore implementation
of supervisor mode RISC-V registers is completely unnecessary.

userspace RISC-V is only permitted to set userspace RISC-V CSRs.

l.

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Re: [libre-riscv-dev] Status on Our RISCV Implementation

[Jacob Lifshay]

On Tue, Mar 24, 2020, 06:59 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:

> On Tue, Mar 24, 2020 at 1:11 PM Immanuel, Yehowshua U
> <yimmanuel3@gatech.edu> wrote:
>
> > > nope.  not for RISC-V.  userspace only.
> >
> > So I guess we’d have a POWER kernel…
>
> correct.  and POWER TLBs and MMU.
>
> > If a binary tries to call RISCV instructions to set supervisor mode
> register - how is that handled?
>
> from userspace? fail... just like any other userspace RISC-V program
> is not permitted to set a supervisor mode register on any standard
> RISC-V system.


However, it's perfectly possible to have software that catches the illegal
instruction traps and emulates them, allowing running a RISC-V kernel.

Jacob
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Re: [libre-riscv-dev] Status on Our RISCV Implementation

[Luke Kenneth Casson Leighton]

On Tuesday, March 24, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:

However, it's perfectly possible to have software that catches the illegal
> instruction traps and emulates them, allowing running a RISC-V kernel.


oh.  yes. good point.  qemu will be doing something like this, i believe?



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