* [libre-riscv-dev] LLHD: Rust is used to drive research in Hardware Design Languages
@ 2020-04-14 23:01 Jacob Lifshay
2020-04-14 23:21 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 4+ messages in thread
From: Jacob Lifshay @ 2020-04-14 23:01 UTC (permalink / raw)
To: Libre-RISCV General Development
Found this very interesting paper on LLHD, a new IR for HDLs, in this
week's This Week in Rust:
https://arxiv.org/pdf/2004.03494
The website is:
http://llhd.io/
Jacob
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* Re: [libre-riscv-dev] LLHD: Rust is used to drive research in Hardware Design Languages
2020-04-14 23:01 [libre-riscv-dev] LLHD: Rust is used to drive research in Hardware Design Languages Jacob Lifshay
@ 2020-04-14 23:21 ` Luke Kenneth Casson Leighton
2020-04-14 23:43 ` Jacob Lifshay
0 siblings, 1 reply; 4+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-04-14 23:21 UTC (permalink / raw)
To: Libre-RISCV General Development
On Wednesday, April 15, 2020, Jacob Lifshay <programmerjake@gmail.com>
wrote:
> Found this very interesting paper on LLHD, a new IR for HDLs, in this
> week's This Week in Rust:
>
> https://arxiv.org/pdf/2004.03494
>
> The website is:
> http://llhd.io/
aw not another one! and did they add it to yosys? if not it is
unfortunately just a toy. yosys is the defacto standard gateway to FPGAs
and ASIC synthesis
l.
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* Re: [libre-riscv-dev] LLHD: Rust is used to drive research in Hardware Design Languages
2020-04-14 23:21 ` Luke Kenneth Casson Leighton
@ 2020-04-14 23:43 ` Jacob Lifshay
2020-04-14 23:49 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 4+ messages in thread
From: Jacob Lifshay @ 2020-04-14 23:43 UTC (permalink / raw)
To: Libre-RISCV General Development
On Tue, Apr 14, 2020, 16:21 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
> On Wednesday, April 15, 2020, Jacob Lifshay <programmerjake@gmail.com>
> wrote:
>
> > Found this very interesting paper on LLHD, a new IR for HDLs, in this
> > week's This Week in Rust:
> >
> > https://arxiv.org/pdf/2004.03494
> >
> > The website is:
> > http://llhd.io/
>
>
> aw not another one! and did they add it to yosys? if not it is
> unfortunately just a toy. yosys is the defacto standard gateway to FPGAs
> and ASIC synthesis
Created an issue for adding RTLIL support:
https://github.com/fabianschuiki/llhd/issues/116
Jacob
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* Re: [libre-riscv-dev] LLHD: Rust is used to drive research in Hardware Design Languages
2020-04-14 23:43 ` Jacob Lifshay
@ 2020-04-14 23:49 ` Luke Kenneth Casson Leighton
0 siblings, 0 replies; 4+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-04-14 23:49 UTC (permalink / raw)
To: Libre-RISCV General Development
On Wednesday, April 15, 2020, Jacob Lifshay <programmerjake@gmail.com>
wrote:
>
>
> Created an issue for adding RTLIL support:
> https://github.com/fabianschuiki/llhd/issues/116
nice.
>
>
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2020-04-14 23:01 [libre-riscv-dev] LLHD: Rust is used to drive research in Hardware Design Languages Jacob Lifshay
2020-04-14 23:21 ` Luke Kenneth Casson Leighton
2020-04-14 23:43 ` Jacob Lifshay
2020-04-14 23:49 ` Luke Kenneth Casson Leighton
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