[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=217

--- Comment #65 from Jean-Paul.Chaput@lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #60)
> (In reply to Jean-Paul.Chaput from comment #59)
> > (In reply to Luke Kenneth Casson Leighton from comment #58)
> > > (In reply to Jean-Paul.Chaput from comment #57)
> > >   File "doAlu16Flat.py", line 89, in build
> > >     result = self.route()
> > >   File "/home/lkcl/soclayout/experiments7/utils.py", line 191, in route
> > >     katana.loadGlobalRouting(Anabatic.EngineLoadGrByNet)
> > > hurricane.HurricaneError: [BUG] Unmanaged Configuration [16843266] =
> > > [2+2+0+1,1+0] <id:1492 Net "a(5)" e-- LOGICAL i--- (IN)> in <id:5325
> > > Anabatic::GCell <Box 200l 0l 250l 50l> ----------M---,i-A- 15>
> > >       The global routing seems to be defective.
> > 
> > Argh! Yes everything was commited. But, as we are not 100% clone of
> > each other (what Intel would call "copy exact" for its foundries),
> > you may have got a slighty different Yosys netlist and so a
> > slightly different placement. 
> 
> iinteresting.  i remember your warning about that on bug #178.
> 
> ahh so in case you need to repro that:
> 
> $ cd ~/yosys
> $ git diff
> diff --git a/Makefile b/Makefile
> index e9dfd9df..8a935579 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -128,7 +128,7 @@ bumpversion:
>  # is just a symlink to your actual ABC working directory, as 'make mrproper'
>  # will remove the 'abc' directory and you do not want to accidentally
>  # delete your work on ABC..
> -ABCREV = 71f2b40
> +ABCREV = default
>  ABCPULL = 1
>  ABCURL ?= https://github.com/berkeley-abc/abc
> 
> > I was lazy, I didn't manage that case.
> > I will do it this evening...
> 
> i'll git pull on yosys and recompile.
> 
> commit ae115fa3aac9acf7534b3f7c08afaa1b86bfc4ad
> Merge: 2b1fb8c0 35990b95
> Author: Claire Wolf <clifford@clifford.at>
> Date:   Mon Apr 20 14:51:40 2020 +0200

I think this is a more wider issue. Throughout all the project, all the
versions
of the tools should be fixed, and when bumped everybody should do it at the
same
time. And when the chip is finished, a full snapshot of all the versions should
be packed alongside the chip source code.

This is the way we did it at LIP6.

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