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From: bugzilla-daemon@libre-riscv.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Date: Mon, 16 Mar 2020 22:01:50 +0000
Message-ID: <bug-217-13-cTONz2UJgT@http.bugs.libre-riscv.org/> (raw)
In-Reply-To: <bug-217-13@http.bugs.libre-riscv.org/>

http://bugs.libre-riscv.org/show_bug.cgi?id=217

--- Comment #7 from Jock Tanner <tanner.of.kha@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> ok, jock, i thought about it: i have a specific task for you :)
> 
> * take benchs/nmigen/ALU16 and create (cut/paste) experiments7
>   in soclayout
> * in doAlu16.py, in each of add(), sub() and alu16(), *replace*
>   the hand-coded addition of Pins (Pin.create) with explicit
>   use of ChipConf from cumulus/src/plugins/chip/Configuration.py
> 
> the only thing to watch out for is that BLOCKAGE2 through BLOCKAGE5
> are added in add() and sub().  it *may* be necessary to create a
> separate function for that, we just have to see.
> 
> if necessary, for now, take a copy of Configuration.py and add it
> to experiments7 in the soclayout repo, so that you can edit it.
> or, better (preferred), subclass it.
> 
> just get stuck in, and see how that goes?

Luke and everybody,

I played with the example for several days, but I afraid I have no answers, but
only more questions.

First of all, I'm not sure what the result of the 'doAlu16.py' script should
be, and how running of the script relates to running 'make' with different
targets. I thought I can find some documents on this, but I couldn't.

I think the script is not working anyway. The most I can get out of it is

> [ERROR] NegociateWindow::createTrackSegment(): No track near axis of <id:7676 Horizontal b(15) METAL2 [320l 400l] [320l 400l] 2l rpD:0 ----UC---T-----ri-tt-> (after adjust).

Is something wrong with my setup?

Oh, and it was only after I fixed an error with forgotten import:

(~/alliance-check-tookit/benchs/nmigen/ALU16/doAlu16.py:523)
>     showPythonTrace( __file__, e, False )

but 'showPythonTrace()' is not defined.

I thought I could get something out of documentation, but it seems very scarce
to me. I could not find an API reference manual (neither Python nor C++), but
then I was starting to think it wouldn't help me either.

It also makes me wonder why all the examples are totally devoid of meaningful
comments or docstrings, as if they aren't meant for didactic purposes, but just
for spinning off new devices. Like boilerplates. Except they are too big for
boilerplates, and not exactly working.

I hope I was able to somehow address the issue of creating the layer Luke
mentions:

https://git.libre-riscv.org/?p=soclayout.git;a=blob;f=experiments7/doAlu16.py;hb=HEAD#l25

But otherwise I am lost. And the overall quality of the Python code I'm dealing
with in Coriolis makes me want to poke my eyes out. I'm terribly sorry if I
offended someone, but at the same time I'm sure I'm not the only one saying
this. I wonder why it is so bad and where to start improving it.

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Thread overview: 87+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-12 11:57 [libre-riscv-dev] [Bug 217] New: " bugzilla-daemon
2020-03-12 16:39 ` [libre-riscv-dev] [Bug 217] " bugzilla-daemon
2020-03-12 16:57 ` bugzilla-daemon
2020-03-12 17:07 ` bugzilla-daemon
2020-03-12 17:24 ` bugzilla-daemon
2020-03-12 17:37 ` bugzilla-daemon
2020-03-13 11:36 ` bugzilla-daemon
2020-03-16 22:01 ` bugzilla-daemon [this message]
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     [not found] <bug-217-13@https.bugs.libre-soc.org/>
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