[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
okaay, i have this:

# Count Trailing Zeros Word

X-Form

* cnttzw RA,RS (Rc=0)
* cnttzw.  RA,RS (Rc=1)

    n <- 0

    do while n < 32
       if (RS)[63-n=] = 0b1 then
            leave
       n  <- n + 1

    RA <- EXTZ64(n)

which gets turned into:

    n = 0
    while n < 64:
        if GPR(RS)[63 - n] == 1:
            break
        n = n + 1
    RA = EXTZ64(n)

that may need to be "self.GPR(RS)" or just
"self.regfile.read_reg(RS")

hmmm nuts, it needs to be more like this, doesn't it?

            r1_sel = yield pdecode2.e.read_reg1.data
            operand1 = self.regfile.read_reg(r1_sel)

because we are pushing things through decode2. that's code from the
internal_ops simulator.

actually... y'know what?  i'm inclined to suggest skipping decode2
for this, because the "Form" (X-Form, etc.) is *already* encoded in
the spec.

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