[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

--- Comment #31 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
i put a comment in where that would need to go:

lkcl@fizzy:~/src/libreriscv/soc/src/soc$ git diff d4c6
diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 5b5e3c1..5b6e158 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -123,17 +123,22 @@ class ISACaller:
     def memassign(self, ea, sz, val):
         self.mem.memassign(ea, sz, val)

-    def prep_namespace(self):
+    def prep_namespace(self, formname, op_fields):
+        # TODO: get field names from form in decoder*1* (not decoder2)
+        # decoder2 is hand-created, and decoder1.sigform is auto-generated
+        # from spec
+        # then "yield" fields only from op_fields rather than hard-coded
+        # list, here.
         for name in ['SI', 'UI', 'D', 'BD']:
             signal = getattr(self.decoder, name)
             val = yield signal
             self.namespace[name] = SelectableInt(val, bits=signal.width)

     def call(self, name):

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