[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=269

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
the basics of the parser now work.

this:

    n  <- 0
    do while n < 64
       if (RS)[63-n] = 0b1 then
            leave
       n  <- n + 1
    RA <- EXTZ64(n)

gets turned into this:

    n = 0
    while n < 64:
        if RS[63 - n] == 1:
            break
        n = n + 1
    RA = EXTZ64(n)

which is executable python code.

one little piece of syntax not currently supported is the regfile read.
(RS) means "look up in the GPR using the bits from the field named RS of
the opcode", not "change the bits in the opcode"

unfortunately, assignment to RT means "change the regfile".

it's a little more non-obvious than at first glance.

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