[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=296

--- Comment #7 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> (In reply to Jacob Lifshay from comment #2)
> > Seems like a good idea, however out-of-order (and in-order) processors
> > depend on single-cycle forwarding between the results of one operation and
> > the input of the next for most of their performance, the forwarding network
> > would need to keep that property (haven't fully thought through if this idea
> > keeps that property).
> 
> luckily, in a Dependency-Matrix-based system, nothing is timing-dependent.
> the DMs (the combination of the FU-Regs and FU-FU matrices) preserve a
> Directed Acyclic Graph of the relationships between all in-flight operations,
> based on the register numbers, *not* based on the time taken to completion
> *of* each operation, in any way.  FSMs, pipelines, async FUs,
> variable-pipelines,
> it's all the same to the 6600-DMs.
> 
> therefore (the point of explaining that is:) it doesn't _actually_ matter if
> the forwarding between result latches at the output side of the Function
> Units
> is delayed even 5-20 cycles in reaching the input latches of the FUs that
> need
> that result.

That's true for correctness, but not for performance. Delaying 20 cycles on
every forwarding operation would seriously reduce the performance, probably by
at least 10x, so, obviously, that should be avoided.

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