[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=296

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
hmm because we are aiming for a minimum 4x FP32 FMACs per cycle,
the datapath situation is much "worse" than i described earlier.
(meaning: the pressure to reduce the amount of control and information
wires is much higher).

* 4x FP32 FMACs is 2x 64-bit results
* however it's also 4x3 *read* registers @ FP32 which is 6x 64-bit
  reads.

having 6R2W on the regfile is completely impractical.

this is why we decided to go for the HI/LO-32-ODD/EVEN regfile split
(and to synchro-"pair" 32-bit operations if 64-bit calculations are
required, using PartitionedSignal).

by subdividing, we effectively end up with *four* separate isolated
32-bit-wide register files.

thus there will be *four* separate Common Data Buses, each serving
32-bit data to a *quarter* of the Function Units, each.

i'll draw it out.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev