[libre-riscv-dev] [Bug 324] New: create POWER9 DIV pipeline

[libre-riscv-dev] [Bug 324] New: create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

            Bug ID: 324
           Summary: create POWER9 DIV pipeline
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

a DIV (and MOD) pipeline is needed similar to the other soc.fu pipelines.

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|lkcl@lkcl.net               |programmerjake@gmail.com
           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=305

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
register allocations, for fu.div.pipe_data.py

looks to be identical to ALUInputData and ALUOutputData.

https://libre-soc.org/openpower/isa/fixedarith/

# Divide

XO-Form   divw* RT,RA,RB

Special Registers Altered:

* CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
* SO OV OV32  (if OE=1)

# Modulo

X-Form  mod* RT,RA,RB

no special regs altered

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_enums.py;hb=HEAD

TODO, add DIV to Function enum, and back in the (annoyingly separated) CSV
files change DIV and MOD operations from type ALU Function Unit to type DIV.

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #3 from Jacob Lifshay <programmerjake@gmail.com> ---
after looking through the spec some, it turns out that div and rem don't
actually trap on division by zero, so that makes them much easier to implement.
The numerical results are undefined on division-by-zero/overflow, so I will
need to run some tests on a Power processor to see which results we should
produce, hopefully they are the same as for RISC-V.

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)
> after looking through the spec some, it turns out that div and rem don't
> actually trap on division by zero, so that makes them much easier to
> implement. The numerical results are undefined on division-by-zero/overflow,
> so I will need to run some tests on a Power processor to see which results
> we should produce, hopefully they are the same as for RISC-V.

good idea.

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #5 from Jacob Lifshay <programmerjake@gmail.com> ---
I wrote a simple Rust program that runs different Power instructions (just div*
and mod* for now) and put the results here:
https://salsa.debian.org/Kazan-team/power-instruction-analyzer/-/blob/master/output-for-initial-2-ga7250d2.txt

Source here:
https://salsa.debian.org/Kazan-team/power-instruction-analyzer

result_prev is assigned to the result register before executing the tested
instruction since sometimes processors just skip writing to a register in
exceptional cases

From what I can tell, for all error cases for div and mod instructions, POWER9
just writes 0 to the result register.

For the instructions with just 32-bit results, from what I can tell from a
relatively small number of test cases, it zero extends for all signed/unsigned
div instructions, zero extends for unsigned mod instructions, and sign extends
for signed mod instructions.

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

Jacob Lifshay <programmerjake@gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|CONFIRMED                   |IN_PROGRESS

--- Comment #6 from Jacob Lifshay <programmerjake@gmail.com> ---
I added a Rust model for the div and rem instructions as well as converted the
output format to JSON since that's waay easier to ingest than the custom output
format I had before. The model matches the native POWER9 instructions for all
the cases I tested.

I also added conditional compilation code that allows running just the model on
any computer rather than just on POWER9:
Run it with:
cargo run --no-default-features

Model functions:
https://salsa.debian.org/Kazan-team/power-instruction-analyzer/-/blob/master/src/instr_models.rs

This should make it easier to copy the behavior of POWER9 in the nmigen div
pipeline.

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #6)
> I added a Rust model for the div and rem instructions as well as converted
> the output format to JSON since that's waay easier to ingest than the custom
> output format I had before.

:)

> This should make it easier to copy the behavior of POWER9 in the nmigen div
> pipeline.

ah fantastic.  yes, looking at microwatt, the synthesis of all the various
options is quite obtuse (and brilliant).

i've found it is essential to have some form of guide in a familiar language.
it's really useful that these are also binary-executable on native POWER9
as well as really clear documented actual implementations.

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #8 from Jacob Lifshay <programmerjake@gmail.com> ---
Created the setup stage that translates from the input data to the format
expected by DivPipeCore but didn't create tests yet, am going to be done for
today. Still have to double check that I got the number of fractional bits
correct.

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #8)
> Created the setup stage that translates from the input data to the format
> expected by DivPipeCore but didn't create tests yet, am going to be done for
> today. Still have to double check that I got the number of fractional bits
> correct.

fantastic.  as you can probably see i'm slowly going through the
test_pipe_caller.py code removing code-duplication.  for now i recommend
cookie-cutting fu/alu/test_pipe_caller.py in its entirety, because i
noticed that these use OE/Rc.  

* divdu RT,RA,RB (OE=0 Rc=0)

Special Registers Altered:

    CR0                     (if Rc=1)
    SO OV OV32             (if OE=1)

that means they're exactly like fixedarith, for *both* input and output
data, so you can straight-cookie-cut alu test_pipe_caller.py

i will drop in an fu/compunits/test/test_div_compunit.py

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[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #9)

> that means they're exactly like fixedarith, for *both* input and output
> data, so you can straight-cookie-cut alu test_pipe_caller.py

dropped in a copy for you (the one that was there already needed
updating).

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Re: [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[Jacob Lifshay]

On Wed, Jun 10, 2020, 04:33 <bugzilla-daemon@libre-soc.org> wrote:

> https://bugs.libre-soc.org/show_bug.cgi?id=324
>
> --- Comment #10 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
> (In reply to Luke Kenneth Casson Leighton from comment #9)
>
> > that means they're exactly like fixedarith, for *both* input and output
> > data, so you can straight-cookie-cut alu test_pipe_caller.py
>
> dropped in a copy for you (the one that was there already needed
> updating).
>

Thanks!

Jacob
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