[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=351

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Cole Poirier from comment #4)
> (In reply to Luke Kenneth Casson Leighton from comment #2)
> > https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=HEAD
> > 
> > saw this.
> 
> Thanks! I'm trying to get something down, so I don't freeze because there
> are multiple things I don't understand.
> 
> > 
> > i think... actually... the list  of ports in the constructor, have to be
> > done manually, then those wired via a mux to the "real" ports
> > 
> > so a for loop adds RecordObjects
> > 
> > ren=1, data=bitwidth/nregs
> > 
> > then appends an *extra* on
> > ren=nregs, data=bitwidth
> 
> Pushed a commit with this change, not sure if it's exactly right yet.

not seen it.

2nd commit needs to add a *SECOND* pair of lists.

to 2nd set, *manually* add RecordObjects.  do not use readport() or writeport()
 function.  *MANUALLY* add multiple RecordObjects.

these are the "external" where the 1st set is "internal".

> > 
> > then in the constructor:

i meant "elaborate" here.

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