[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=351

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
ok so first derive from RegFileArray.

use the two parameters as follows:

* bitwidth: the TOTAL number of bits
* n_regs: the number of subdivisions of those bits.

therefore RegfileArray n_regs = nregs

however RegfileArray regwidth is bitwidth DIVIDED by n_regs.

then, in the constructor, add n_regs read ports and n_regs write ports to a
pair of lists.

you can see this being done in soc.regfile.regfiles here

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;h=d6f3a8dd79930d1286c72a42328363d9b9b8e9f3;hb=HEAD#l42

except, that should be a for loop


next, we want an EXTRA read port and an extra write port.

this should, for data, instead of being only bitwidth/nregs wide, should
instead be the FULL bitwidth wide. 

however the enable lines should be nregs wide.

39         port = RecordObject([("ren", nregs),
  40                              ("data_o", bitwidth)],
  41                             name=name)

like that.


then, in the elaborate:

* if any of the "extra" port ren bits are set, the data is sent through the
corresponding *lower* indexed ports.

you see how that works?

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