[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=351

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
ok i am more awake.  started on adding the virtual port aaaand... spangg, i
ran smack into a pre-existing very close approximation of the virtual port,
in the form of RegFileArray.

*face-palm*.

the way that RegFileArray works is: it creates an array of registers,
then when read_port (or write_port) is called, an *array* of individual
read/write ports - one for each individual register - is returned, *and*
a "global" access port is provided.

that global access port is a "broadcast bus" to every register, and its
width is the *exact* same width as the register width.

also, where each register has a 1-bit-wide ren/wen, the global port is
the *accumulation* of all those signals (using self._get_en_sig) in a
unary sequence.

thus, if you pass in say a global.ren="0b00001011", this will read out the OR
of registers numbered 0, 1 *and* 3 (!!) as in:

    result = reg[0] ORed with reg[1] ORed with reg[3]

this will be a regwidth-wide result

what we want, for the virtual port is:

    result = reg[0] CATted with reg[1] CATted with reg[2] CATed with reg[3]...

this will be a regwidth TIMES n_regs wide result

which is very different.

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