[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile - bugzilla-daemon

From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
Date: Tue, 26 May 2020 16:41:00 +0000
Message-ID: <bug-351-13-IADCrzzurI@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-351-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=351

--- Comment #11 from Cole Poirier <colepoirier@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/virtual_port.
> py;hb=HEAD
> 
> i think i have it.  i had to modify RegFileArray to first get it to give me
> only (an array of) read/write ports to each (small) register.
> 
> however... *this is not the full story*!
> 
> we need to prevent and prohibit RegFileArray.read_port() and
> RegFileArray.write_port() from having a "bypass" on the registers
> 
> this is complicated.

I take it you've got this bug under control and I should move on to something
else today? :)

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev