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* [libre-riscv-dev] Following the PowerISA
@ 2020-04-06  2:46 Immanuel, Yehowshua U
  2020-04-06  2:51 ` Immanuel, Yehowshua U
  2020-04-06 10:51 ` Luke Kenneth Casson Leighton
  0 siblings, 2 replies; 7+ messages in thread
From: Immanuel, Yehowshua U @ 2020-04-06  2:46 UTC (permalink / raw)
  To: Libre-RISCV General Development

On the website, we have:

> The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name of the project implies, 
> we will be following the RISC-V ISA due to it being open-source and also because of the huge 
> software and hardware ecosystem building around it. 

Since we are now doing userspace RISCV+POWER and system-wide POWER, I imagine this section should be updated?
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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [libre-riscv-dev] Following the PowerISA
  2020-04-06  2:46 [libre-riscv-dev] Following the PowerISA Immanuel, Yehowshua U
@ 2020-04-06  2:51 ` Immanuel, Yehowshua U
  2020-04-06  3:40   ` Immanuel, Yehowshua U
  2020-04-06 10:58   ` Luke Kenneth Casson Leighton
  2020-04-06 10:51 ` Luke Kenneth Casson Leighton
  1 sibling, 2 replies; 7+ messages in thread
From: Immanuel, Yehowshua U @ 2020-04-06  2:51 UTC (permalink / raw)
  To: Libre-RISCV General Development

Also on the website we have: https://libre-riscv.org/resources/#index9h1


TODO get in touch: Other RISC-V GPU attempts
• https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32

• http://bjump.org/manycore/

• https://resharma.github.io/RISCV32-GPU/


Did we ever contact them? Should I do that?

Yehowshua
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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [libre-riscv-dev] Following the PowerISA
  2020-04-06  2:51 ` Immanuel, Yehowshua U
@ 2020-04-06  3:40   ` Immanuel, Yehowshua U
  2020-04-06  6:28     ` Immanuel, Yehowshua U
  2020-04-06 10:58   ` Luke Kenneth Casson Leighton
  1 sibling, 1 reply; 7+ messages in thread
From: Immanuel, Yehowshua U @ 2020-04-06  3:40 UTC (permalink / raw)
  To: Libre-RISCV General Development

As you can probably tell, I’m going through the resources page and organizing it.

I found a broken link:

https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md

I’m assuming it refers to this?

https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc

If so, I’ll just replace it with a GitHub commit-based link - more permanent.

Yehowshua


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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [libre-riscv-dev] Following the PowerISA
  2020-04-06  3:40   ` Immanuel, Yehowshua U
@ 2020-04-06  6:28     ` Immanuel, Yehowshua U
  2020-04-06  7:02       ` Jacob Lifshay
  0 siblings, 1 reply; 7+ messages in thread
From: Immanuel, Yehowshua U @ 2020-04-06  6:28 UTC (permalink / raw)
  To: Libre-RISCV General Development

https://libre-riscv.org/resources/

I’ve finished going through all the links on the resources page and performed a massive re-organization(basically moved links around into neat sections), and added a couple sections based on my research into the user demographic of POWER systems.

Request for comments…

Yehowshua
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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [libre-riscv-dev] Following the PowerISA
  2020-04-06  6:28     ` Immanuel, Yehowshua U
@ 2020-04-06  7:02       ` Jacob Lifshay
  0 siblings, 0 replies; 7+ messages in thread
From: Jacob Lifshay @ 2020-04-06  7:02 UTC (permalink / raw)
  To: Libre-RISCV General Development

On Sun, Apr 5, 2020, 23:29 Immanuel, Yehowshua U <yimmanuel3@gatech.edu>
wrote:

> https://libre-riscv.org/resources/
>
> I’ve finished going through all the links on the resources page and
> performed a massive re-organization(basically moved links around into neat
> sections), and added a couple sections based on my research into the user
> demographic of POWER systems.
>
> Request for comments…
>

Generally looks good to me!

I have published simple-soft-float, so have updated the IEEE754 section
with links. Also updated to state that both simple-soft-float and Berkeley
softfloat are libraries for emulating IEEE754 in software, only Berkeley
testfloat is software for testing FP implementations.

https://libre-riscv.org/resources/#ieee754testingemulation

Jacob
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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [libre-riscv-dev] Following the PowerISA
  2020-04-06  2:46 [libre-riscv-dev] Following the PowerISA Immanuel, Yehowshua U
  2020-04-06  2:51 ` Immanuel, Yehowshua U
@ 2020-04-06 10:51 ` Luke Kenneth Casson Leighton
  1 sibling, 0 replies; 7+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-04-06 10:51 UTC (permalink / raw)
  To: Libre-RISCV General Development

On Mon, Apr 6, 2020 at 3:46 AM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:
>
> On the website, we have:
>
> > The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name of the project implies,
> > we will be following the RISC-V ISA due to it being open-source and also because of the huge
> > software and hardware ecosystem building around it.
>
> Since we are now doing userspace RISCV+POWER and system-wide POWER, I imagine this section should be updated?

https://git.libre-riscv.org/?p=crowdsupply.git;a=commitdiff;h=69576cbd0ca58e98ebbf525d827b377fe7ad04fc

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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [libre-riscv-dev] Following the PowerISA
  2020-04-06  2:51 ` Immanuel, Yehowshua U
  2020-04-06  3:40   ` Immanuel, Yehowshua U
@ 2020-04-06 10:58   ` Luke Kenneth Casson Leighton
  1 sibling, 0 replies; 7+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-04-06 10:58 UTC (permalink / raw)
  To: Libre-RISCV General Development

On Mon, Apr 6, 2020 at 3:54 AM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:
>
> Also on the website we have: https://libre-riscv.org/resources/#index9h1
>
>
> TODO get in touch: Other RISC-V GPU attempts
> • https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32

the fossi foundation is run in... "Abusive Contributor Covenant
Conduct Mode" and they have unfortunately... abused that unethical
"Code".  therefore, sadly, the less we have to do with them, the
better.

> • http://bjump.org/manycore/
>
> • https://resharma.github.io/RISCV32-GPU/


> Did we ever contact them?

no.

> Should I do that?

i left the links there mostly to let people know that they exist, so
that there is a comparison.  i did however reach out to the opencores
non-shader-engine team.

this should probably be added as well
https://opencores.org/projects/wf3d
https://opencores.org/projects/opengfx430

oh.  must record this one somewhere
https://opencores.org/projects/video_systems

where the heck is it...

oo!
https://opencores.org/projects/gpu

hm, sorry, can't find it at the moment.  it was a non-shader design.

l.

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^ permalink raw reply	[flat|nested] 7+ messages in thread

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Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-06  2:46 [libre-riscv-dev] Following the PowerISA Immanuel, Yehowshua U
2020-04-06  2:51 ` Immanuel, Yehowshua U
2020-04-06  3:40   ` Immanuel, Yehowshua U
2020-04-06  6:28     ` Immanuel, Yehowshua U
2020-04-06  7:02       ` Jacob Lifshay
2020-04-06 10:58   ` Luke Kenneth Casson Leighton
2020-04-06 10:51 ` Luke Kenneth Casson Leighton

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