* [libre-riscv-dev] daily kan-ban update, 22jul2020 @ 2020-07-23 0:13 Jacob Lifshay 2020-07-23 1:53 ` Cole Poirier 2020-07-23 2:29 ` Luke Kenneth Casson Leighton 0 siblings, 2 replies; 8+ messages in thread From: Jacob Lifshay @ 2020-07-23 0:13 UTC (permalink / raw) To: Libre-RISCV General Development today: still working on Div FSM -- I think it's complete (except for not supporting cancellation), but didn't thoroughly test it yet. In the process of refactoring test_pipe_caller.py into a easier-to-test shape and adding parallel test cases for DivPipeCore, FSMDivCore, and SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 / 0x32867d69), the pipeline (SimOnly) is giving the correct results (rt=0x3), it's the ISA simulator code that's messed up (rt=0xFFFFFFFF). Luke (or whoever is more familiar with it), I'll let you figure out how to fix the ISA simulator. Jacob _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [libre-riscv-dev] daily kan-ban update, 22jul2020 2020-07-23 0:13 [libre-riscv-dev] daily kan-ban update, 22jul2020 Jacob Lifshay @ 2020-07-23 1:53 ` Cole Poirier 2020-07-23 2:29 ` Luke Kenneth Casson Leighton 1 sibling, 0 replies; 8+ messages in thread From: Cole Poirier @ 2020-07-23 1:53 UTC (permalink / raw) To: Libre-RISCV General Development Today: * Finished coriolis2-chroot setup script, it's tested and works correctly! * Finished updating the wiki libreriscv/HDL_workflow/coriolis2 documentation to sync it with the coriolis-chroot setup script I can't push my commit to the libreriscv repo, can you please grant me access Luke? Cole _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [libre-riscv-dev] daily kan-ban update, 22jul2020 2020-07-23 0:13 [libre-riscv-dev] daily kan-ban update, 22jul2020 Jacob Lifshay 2020-07-23 1:53 ` Cole Poirier @ 2020-07-23 2:29 ` Luke Kenneth Casson Leighton 2020-07-23 9:40 ` Luke Kenneth Casson Leighton 1 sibling, 1 reply; 8+ messages in thread From: Luke Kenneth Casson Leighton @ 2020-07-23 2:29 UTC (permalink / raw) To: Libre-RISCV General Development On Thursday, July 23, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote: > today: > still working on Div FSM -- I think it's complete (except for not > supporting cancellation), but didn't thoroughly test it yet. In the > process of refactoring test_pipe_caller.py into a easier-to-test shape > and adding parallel test cases for DivPipeCore, FSMDivCore, and > SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 / > 0x32867d69), the pipeline (SimOnly) is giving the correct results > (rt=0x3), it's the ISA simulator code that's messed up > (rt=0xFFFFFFFF). please raise a bugreport for it. > > Luke (or whoever is more familiar with it), I'll let you figure out > how to fix the ISA simulator. it's running the pseudocode. if the pseudocode gives the wrong answer, that's bad. what happens when testing the same values in simulator/test_div_dim.py? hm wait you can't put initial regs into qemu yet. been meaning to add that. l. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [libre-riscv-dev] daily kan-ban update, 22jul2020 2020-07-23 2:29 ` Luke Kenneth Casson Leighton @ 2020-07-23 9:40 ` Luke Kenneth Casson Leighton 2020-07-23 16:31 ` Jacob Lifshay 0 siblings, 1 reply; 8+ messages in thread From: Luke Kenneth Casson Leighton @ 2020-07-23 9:40 UTC (permalink / raw) To: Libre-RISCV General Development On Thursday, July 23, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote: > > > On Thursday, July 23, 2020, Jacob Lifshay <programmerjake@gmail.com> > wrote: > >> >> SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 / >> 0x32867d69), the pipeline (SimOnly) is giving the correct results >> (rt=0x3), it's the ISA simulator code that's messed up >> (rt=0xFFFFFFFF). > > > please raise a bugreport for it. > saw it, thank you for doing that. these look great btw https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=78096b62db0345846cca70ab2f75f9c3519006c4 -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [libre-riscv-dev] daily kan-ban update, 22jul2020 2020-07-23 9:40 ` Luke Kenneth Casson Leighton @ 2020-07-23 16:31 ` Jacob Lifshay 2020-07-23 16:42 ` Luke Kenneth Casson Leighton 0 siblings, 1 reply; 8+ messages in thread From: Jacob Lifshay @ 2020-07-23 16:31 UTC (permalink / raw) To: Libre-RISCV General Development On Thu, Jul 23, 2020, 02:40 Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote: > On Thursday, July 23, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net> > wrote: > > > > > > > On Thursday, July 23, 2020, Jacob Lifshay <programmerjake@gmail.com> > > wrote: > > > >> > >> SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 / > >> 0x32867d69), the pipeline (SimOnly) is giving the correct results > >> (rt=0x3), it's the ISA simulator code that's messed up > >> (rt=0xFFFFFFFF). > > > > > > please raise a bugreport for it. > > > > saw it, thank you for doing that. > > these look great btw > > > > https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=78096b62db0345846cca70ab2f75f9c3519006c4 Thanks! I used the same list of test values as in power-instruction-analyzer. Jacob _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [libre-riscv-dev] daily kan-ban update, 22jul2020 2020-07-23 16:31 ` Jacob Lifshay @ 2020-07-23 16:42 ` Luke Kenneth Casson Leighton 2020-07-23 17:06 ` Jacob Lifshay 0 siblings, 1 reply; 8+ messages in thread From: Luke Kenneth Casson Leighton @ 2020-07-23 16:42 UTC (permalink / raw) To: Libre-RISCV General Development On Thursday, July 23, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote: > On Thu, Jul 23, 2020, 02:40 Luke Kenneth Casson Leighton <lkcl@lkcl.net> > wrote: > > > On Thursday, July 23, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net> > > wrote: > > > > > > > > > > > On Thursday, July 23, 2020, Jacob Lifshay <programmerjake@gmail.com> > > > wrote: > > > > > >> > > >> SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 / > > >> 0x32867d69), the pipeline (SimOnly) is giving the correct results > > >> (rt=0x3), it's the ISA simulator code that's messed up > > >> (rt=0xFFFFFFFF). > > > > > > > > > please raise a bugreport for it. > > > > > > > saw it, thank you for doing that. > > > > these look great btw > > > > > > > > https://git.libre-soc.org/?p=soc.git;a=commitdiff;h= > 78096b62db0345846cca70ab2f75f9c3519006c4 > > > Thanks! I used the same list of test values as in > power-instruction-analyzer. i wondered if, like in the ieee754fp tests, if some random values could be added, too. also, some exponentially scaled numbers. two random uniform distributed numbers for div, the answer pretty much averages out to 1 which is of course a fairly useless test. by doing this you get a much better distribution suited to testing divide full range: x = random(1,32) return random(0,1<<x) l. > Jacob > _______________________________________________ > libre-riscv-dev mailing list > libre-riscv-dev@lists.libre-riscv.org > http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev > -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [libre-riscv-dev] daily kan-ban update, 22jul2020 2020-07-23 16:42 ` Luke Kenneth Casson Leighton @ 2020-07-23 17:06 ` Jacob Lifshay 2020-07-23 17:11 ` Luke Kenneth Casson Leighton 0 siblings, 1 reply; 8+ messages in thread From: Jacob Lifshay @ 2020-07-23 17:06 UTC (permalink / raw) To: Libre-RISCV General Development On Thu, Jul 23, 2020, 09:42 Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote: > On Thursday, July 23, 2020, Jacob Lifshay <programmerjake@gmail.com> > wrote: > > > On Thu, Jul 23, 2020, 02:40 Luke Kenneth Casson Leighton <lkcl@lkcl.net> > > wrote: > > > > > On Thursday, July 23, 2020, Luke Kenneth Casson Leighton < > lkcl@lkcl.net> > > > wrote: > > > > > > > > > > > > > > > On Thursday, July 23, 2020, Jacob Lifshay <programmerjake@gmail.com> > > > > wrote: > > > > > > > >> > > > >> SimOnly, I discovered that for test_divwuo_regression_1 (0xc4e32b68 > / > > > >> 0x32867d69), the pipeline (SimOnly) is giving the correct results > > > >> (rt=0x3), it's the ISA simulator code that's messed up > > > >> (rt=0xFFFFFFFF). > > > > > > > > > > > > please raise a bugreport for it. > > > > > > > > > > saw it, thank you for doing that. > > > > > > these look great btw > > > > > > > > > > > > https://git.libre-soc.org/?p=soc.git;a=commitdiff;h= > > 78096b62db0345846cca70ab2f75f9c3519006c4 > > > > > > Thanks! I used the same list of test values as in > > power-instruction-analyzer. > > > i wondered if, like in the ieee754fp tests, if some random values could be > added, too. > I specifically want the test cases to be reproducible for power-instruction-analyzer, since the test results generated on a POWER9 cpu are checked into the repo for those who don't have a POWER9. for soc, we can copy the test case generation logic from DivPipeCore's tests in ieee754fpu since that covers waaay more cases (nicely exponentially distributed too) but is also deterministic. it covers the cases: for all 0 <= a < 2^8 and 0 <= b < 64: the case a << b if b < 64 - 8 and the case ~(a << b) if b < 64 - 8 and the case (1 << b) - 1 and the case ~((1 << b) - 1) It might use a different value than 8 -- icr. this covers all the corner cases I can think of, which random testing has a very small chance of ever hitting (small enough that you'd need every person on the planet to all run the test on the order of a billion times each to hit the case once). Jacob _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [libre-riscv-dev] daily kan-ban update, 22jul2020 2020-07-23 17:06 ` Jacob Lifshay @ 2020-07-23 17:11 ` Luke Kenneth Casson Leighton 0 siblings, 0 replies; 8+ messages in thread From: Luke Kenneth Casson Leighton @ 2020-07-23 17:11 UTC (permalink / raw) To: Libre-RISCV General Development On Thursday, July 23, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote: > > for soc, we can copy the test case generation logic from DivPipeCore's > tests in ieee754fpu since that covers waaay more cases (nicely > exponentially distributed too) but is also deterministic. it covers the > cases: > for all 0 <= a < 2^8 and 0 <= b < 64: > the case a << b if b < 64 - 8 > and the case ~(a << b) if b < 64 - 8 > and the case (1 << b) - 1 > and the case ~((1 << b) - 1) ohh yeh i remember now. > It might use a different value than 8 -- icr. > > this covers all the corner cases I can think of, which random testing has a > very small chance of ever hitting yehyeh this is why the ieee754fp tests have to have special cornercase handling, zero, inf, nan etc. (small enough that you'd need every > person on the planet to all run the test on the order of a billion times > each to hit the case once). :) we need a way to express these, cross language, so that they can be run in multiple scenarios. qemu, pia, ISACaller, HDL. l. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, back to index Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-07-23 0:13 [libre-riscv-dev] daily kan-ban update, 22jul2020 Jacob Lifshay 2020-07-23 1:53 ` Cole Poirier 2020-07-23 2:29 ` Luke Kenneth Casson Leighton 2020-07-23 9:40 ` Luke Kenneth Casson Leighton 2020-07-23 16:31 ` Jacob Lifshay 2020-07-23 16:42 ` Luke Kenneth Casson Leighton 2020-07-23 17:06 ` Jacob Lifshay 2020-07-23 17:11 ` Luke Kenneth Casson Leighton
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