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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: "Herrenschmidt, Benjamin" <benh@amazon.com>
Cc: "openpower-hdl-cores@mailinglist.openpowerfoundation.org"
	<openpower-hdl-cores@mailinglist.openpowerfoundation.org>,
	"libre-riscv-dev@lists.libre-riscv.org"
	<libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode
Date: Mon, 3 Aug 2020 02:00:49 +0100
Message-ID: <CAPweEDxNzKwFdCG1PvbMDHqYa_LzpJyN0sQF8LNYDir=sUWcOw@mail.gmail.com> (raw)
In-Reply-To: <ecbdd6b08e1937fa1d6b953add782909e4db8015.camel@amazon.com>

On Monday, August 3, 2020, Herrenschmidt, Benjamin <benh@amazon.com> wrote:

>
> > is there a standard for DMI address bus locations?
>
> Not really... I just made it all up :-)


that's funny, i like it :)

can we collaborate on making some more up, for example adding CR, XER and
the remaining SPRs to the list of registers?

also bear in mind, FP regs may get added (to microwatt).  and that in
libresoc we intend to expand the scalar int and fp regs to 128 entries.

l.



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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-31 14:40 Luke Kenneth Casson Leighton
2020-08-01 13:55 ` Luke Kenneth Casson Leighton
2020-08-03  0:13   ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Herrenschmidt, Benjamin
2020-08-03  1:00     ` Luke Kenneth Casson Leighton [this message]
2020-08-03  1:05       ` Benjamin Herrenschmidt
2020-08-03  1:35         ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-08-03  1:39           ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Herrenschmidt, Benjamin
2020-08-03  2:38             ` [libre-riscv-dev] " Luke Kenneth Casson Leighton

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