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From: "Herrenschmidt, Benjamin" <benh@amazon.com>
To: "lkcl@lkcl.net" <lkcl@lkcl.net>,
	"openpower-hdl-cores@mailinglist.openpowerfoundation.org"
	<openpower-hdl-cores@mailinglist.openpowerfoundation.org>
Cc: "libre-riscv-dev@lists.libre-riscv.org"
	<libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt feature request: "switch off all optimisations" mode
Date: Mon, 3 Aug 2020 00:13:55 +0000
Message-ID: <ecbdd6b08e1937fa1d6b953add782909e4db8015.camel@amazon.com> (raw)
In-Reply-To: <CAPweEDzFJH4MeTGHaHOj0++5ZbntYgWNMkMs8VDVFK1anA_2=w@mail.gmail.com>

On Sat, 2020-08-01 at 14:55 +0100, Luke Kenneth Casson Leighton wrote:
> 
> 
> On Friday, July 31, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net
> > wrote:
> > what would you suggest here? how can we "single-step" microwatt? 
> > clearly performance is not important: cycle-accurate comparisons is
> > the goal.
> > 
> 
> i since realised that the DMI interface serves this purpose, and
> investigated core_debug.vhdl
>  
> with a little bit (or a lot) of futzing about with a FSM i should be
> able to run a single instruction then cycle through all of the GPRs,
> PC and MSR, dumping them out.
> 
> by implementing the same interface in libresoc i can do a cycle by
> cycle comparison and find the discrepancies.
> 
> it would be particularly useful to be able to get at the SPRs and the
> CR as well, this way.
> 
> is there a standard for DMI address bus locations?

Not really... I just made it all up :-)

Cheers,
Ben.

> l 
> 
> 
> 
> _______________________________________________
> OpenPOWER-HDL-Cores mailing list
> OpenPOWER-HDL-Cores@mailinglist.openpowerfoundation.org
> 
http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores
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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-31 14:40 [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-08-01 13:55 ` Luke Kenneth Casson Leighton
2020-08-03  0:13   ` Herrenschmidt, Benjamin [this message]
2020-08-03  1:00     ` Luke Kenneth Casson Leighton
2020-08-03  1:05       ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Benjamin Herrenschmidt
2020-08-03  1:35         ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-08-03  1:39           ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Herrenschmidt, Benjamin
2020-08-03  2:38             ` [libre-riscv-dev] " Luke Kenneth Casson Leighton

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