From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: "openpower-hdl-cores@mailinglist.openpowerfoundation.org"
<openpower-hdl-cores@mailinglist.openpowerfoundation.org>
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode
Date: Sat, 1 Aug 2020 14:55:27 +0100
Message-ID: <CAPweEDzFJH4MeTGHaHOj0++5ZbntYgWNMkMs8VDVFK1anA_2=w@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDw+-AKRy9jB8Q6E-QiQ+OhM-BS4HizgAsh37buVd+Y0Gg@mail.gmail.com>
On Friday, July 31, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
>
> what would you suggest here? how can we "single-step" microwatt? clearly
> performance is not important: cycle-accurate comparisons is the goal.
>
i since realised that the DMI interface serves this purpose, and
investigated core_debug.vhdl
with a little bit (or a lot) of futzing about with a FSM i should be able
to run a single instruction then cycle through all of the GPRs, PC and MSR,
dumping them out.
by implementing the same interface in libresoc i can do a cycle by cycle
comparison and find the discrepancies.
it would be particularly useful to be able to get at the SPRs and the CR as
well, this way.
is there a standard for DMI address bus locations?
l
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-31 14:40 Luke Kenneth Casson Leighton
2020-08-01 13:55 ` Luke Kenneth Casson Leighton [this message]
2020-08-03 0:13 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Herrenschmidt, Benjamin
2020-08-03 1:00 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-08-03 1:05 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Benjamin Herrenschmidt
2020-08-03 1:35 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-08-03 1:39 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Herrenschmidt, Benjamin
2020-08-03 2:38 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
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