From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Cc: "openpower-hdl-cores@mailinglist.openpowerfoundation.org"
<openpower-hdl-cores@mailinglist.openpowerfoundation.org>
Subject: Re: [libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode
Date: Mon, 3 Aug 2020 02:35:40 +0100
Message-ID: <CAPweEDyEo9YjQBMLQDgdsn9gFbRi1OMuKMmjUida_vGsLD5sqg@mail.gmail.com> (raw)
In-Reply-To: <ef44d4fe97ab91f802f29e57212bdd3c0a7bdadf.camel@kernel.crashing.org>
On Monday, August 3, 2020, Benjamin Herrenschmidt <benh@kernel.crashing.org>
wrote:
> On Mon, 2020-08-03 at 02:00 +0100, Luke Kenneth Casson Leighton wrote:
> >
> >
> > On Monday, August 3, 2020, Herrenschmidt, Benjamin <benh@amazon.com>
> > wrote:
> > > > is there a standard for DMI address bus locations?
> > >
> > > Not really... I just made it all up :-)
> >
> > that's funny, i like it :)
> >
> > can we collaborate on making some more up, for example adding CR, XER
> > and the remaining SPRs to the list of registers?
>
> Sure. Patches welcome ;-)
ah i was thinking more along the lines of agreeing a spec that suits both
teams, even if the definitions are reserved for later implementation.
(btw we've an october tapeout deadline and i am not yet a vhdl developer).
by agreeing a set of registers, future teams with their own implementation
will want to save development effort and conform to the same spec.
Also check out Paul's WIP branches, he also
> occasionally add stuff.
willdo.
>
> > also bear in mind, FP regs may get added (to microwatt). and that in
> > libresoc we intend to expand the scalar int and fp regs to 128
> > entries.
>
> Paul has some of that in his FPU work already.
ah excellent.
--
---
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Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-31 14:40 Luke Kenneth Casson Leighton
2020-08-01 13:55 ` Luke Kenneth Casson Leighton
2020-08-03 0:13 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Herrenschmidt, Benjamin
2020-08-03 1:00 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-08-03 1:05 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Benjamin Herrenschmidt
2020-08-03 1:35 ` Luke Kenneth Casson Leighton [this message]
2020-08-03 1:39 ` Herrenschmidt, Benjamin
2020-08-03 2:38 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
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