From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Cc: "openpower-hdl-cores@mailinglist.openpowerfoundation.org"
<openpower-hdl-cores@mailinglist.openpowerfoundation.org>,
"libre-riscv-dev@lists.libre-riscv.org"
<libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt feature request: "switch off all optimisations" mode
Date: Mon, 03 Aug 2020 11:05:00 +1000
Message-ID: <ef44d4fe97ab91f802f29e57212bdd3c0a7bdadf.camel@kernel.crashing.org> (raw)
In-Reply-To: <CAPweEDxNzKwFdCG1PvbMDHqYa_LzpJyN0sQF8LNYDir=sUWcOw@mail.gmail.com>
On Mon, 2020-08-03 at 02:00 +0100, Luke Kenneth Casson Leighton wrote:
>
>
> On Monday, August 3, 2020, Herrenschmidt, Benjamin <benh@amazon.com>
> wrote:
> > > is there a standard for DMI address bus locations?
> >
> > Not really... I just made it all up :-)
>
> that's funny, i like it :)
>
> can we collaborate on making some more up, for example adding CR, XER
> and the remaining SPRs to the list of registers?
Sure. Patches welcome ;-) Also check out Paul's WIP branches, he also
occasionally add stuff.
> also bear in mind, FP regs may get added (to microwatt). and that in
> libresoc we intend to expand the scalar int and fp regs to 128
> entries.
Paul has some of that in his FPU work already.
Cheers,
Ben.
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Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-31 14:40 [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-08-01 13:55 ` Luke Kenneth Casson Leighton
2020-08-03 0:13 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Herrenschmidt, Benjamin
2020-08-03 1:00 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-08-03 1:05 ` Benjamin Herrenschmidt [this message]
2020-08-03 1:35 ` Luke Kenneth Casson Leighton
2020-08-03 1:39 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Herrenschmidt, Benjamin
2020-08-03 2:38 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
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