[libre-riscv-dev] [Bug 288] New: intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[libre-riscv-dev] [Bug 288] New: intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=288

            Bug ID: 288
           Summary: intro post for powerpc-notebook.org and
                    https://www.powerprogress.org/en/
           Product: Libre-RISC-V Website
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: website
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

Roberto from PowerPC-notebook and PowerProgress Community says:

"Regarding starting with cross links in our websites to our projects, from our
side  we can start with a short post that can  intro https://libre-soc.org/
project.  if you and your team will provide a short text I will publish next
days."

what would we like to have on the news page of powerprogress.org?

and, what should we put on libre-soc?

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[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=288

Yehowshua <yimmanuel3@gatech.edu> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |yimmanuel3@gatech.edu

--- Comment #1 from Yehowshua <yimmanuel3@gatech.edu> ---
Something Like This:

LibreSOC is an Open Hardware and Open Software project that aims to deliver a
physical quad core 180nm POWER compliant SOC that comes complete with a CPU,
GPU, VPU, and DDR controller. All the software and hardware from the drivers
down to the RTL and VLSI cells are open. LibreSOC is also providing the
necessary drivers amongst which include Vulkan and OpenCL drivers.

The intended market includes customers who desire acceleration in the embedded
space without relying on ARM's proprietary drivers that have been know to break
in the past.

I'll figure out what to put on LibreSOC soon.

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[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=288

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Yehowshua from comment #1)
> Something Like This:
> 
> LibreSOC is an Open Hardware and Open Software project that aims to deliver
> a physical quad core 180nm POWER compliant SOC that comes complete with a

no, single-core.  we're not doing quad-core, it will require something
like 160 mm^2 and that would cost around USD $60,000 just on its own.
not to mention, the power consumption would be immense, well beyond
what a standard low-cost JEDEC QFP package could handle.

we're keeping it to single-core, no SMP, no L2 cache.
https://libre-soc.org/3d_gpu/180nm_single_core_testasic_memlayout.jpg

the *next* version is quad-core, 28-45nm, full SMP.

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[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=288

--- Comment #3 from Yehowshua <yimmanuel3@gatech.edu> ---
Ah I see. That makes sense to me.

So this:

LibreSOC is an Open Hardware and Open Software project that aims to deliver a
physical  POWER compliant SOC that comes complete with a CPU, GPU, VPU, and DDR
controller. All the software and hardware from the drivers down to the RTL and
VLSI cells are open. LibreSOC is also providing the necessary drivers amongst
which include Vulkan and OpenCL drivers.

The intended market includes customers who desire acceleration in the embedded
space without relying on ARM's proprietary drivers that have been know to break
in the past.

The first iteration of LibreSOC targets a single-core at 180nm. Subsequent
generations target more cores at a smaller node size.

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[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=288

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Yehowshua from comment #3)
> Ah I see. That makes sense to me.
> 
> So this:
> 
> LibreSOC is an Open Hardware and Open Software project that aims to deliver
> a physical  POWER compliant SOC that comes complete with a CPU, GPU, VPU,
> and DDR controller. All the software and hardware from the drivers down to
> the RTL and VLSI cells are open. 

libre-licensed.  "open" leaves the possibility of accusations of "fake open
source".

"we'll release the code when it's revision 1.0... but it's open!".

"we'll release the code when it's ready... but it's open!"

"we'll release the code... under a non-commercial license... but it's open!"

> LibreSOC is also providing the necessary
> drivers amongst which include Vulkan and OpenCL drivers.

no, not OpenCL.  that has to come later as we'll need an entire new
grant to do it.

> The intended market includes customers who desire acceleration in the
> embedded space without relying on ARM's proprietary drivers that have been
> know to break in the past.

and piss people off :)

> The first iteration of LibreSOC targets a single-core at 180nm. Subsequent
> generations target more cores at a smaller node size.

looks good.  i'd put "target multiple SMP cores" though.  "more cores"
could mean "NUMA" or "SIMT".  SIMT is almost impossible to program for
general-purpose, and NUMA is a royal pain, memory-wise.

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[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=288

Jacob Lifshay <programmerjake@gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |programmerjake@gmail.com

--- Comment #5 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> > The first iteration of LibreSOC targets a single-core at 180nm. Subsequent
> > generations target more cores at a smaller node size.
> 
> looks good.  i'd put "target multiple SMP cores" though.  "more cores"
> could mean "NUMA" or "SIMT".  SIMT is almost impossible to program for
> general-purpose, and NUMA is a royal pain, memory-wise.

Sounds good, though, it would be NUMA if we have multiple chips wired together
using OmniXpress or similar.


Also, we should be consistent spelling Libre-SOC with the hyphen like we
agreed.

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[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=288

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #5)
> (In reply to Luke Kenneth Casson Leighton from comment #4)
> > > The first iteration of LibreSOC targets a single-core at 180nm. Subsequent
> > > generations target more cores at a smaller node size.
> > 
> > looks good.  i'd put "target multiple SMP cores" though.  "more cores"
> > could mean "NUMA" or "SIMT".  SIMT is almost impossible to program for
> > general-purpose, and NUMA is a royal pain, memory-wise.
> 
> Sounds good, though, it would be NUMA if we have multiple chips wired
> together using OmniXpress or similar.

true


> Also, we should be consistent spelling Libre-SOC with the hyphen like we
> agreed.

good catch.

Libre-SOC is a Libre Hardware-Software project that aims to deliver a physical 
POWER compliant SOC that comes complete with a CPU, GPU, VPU, and DDR
controller. All the software and hardware from the drivers down to the RTL and
VLSI cells are libre-licensed. Libre-SOC is also providing the necessary
drivers amongst which include Kazan (a Vulkan 3D driver) and the full
bootloader and on-board boot firmware source.

The intended market includes customers who desire acceleration in the embedded
space without relying on ARM or 3rd party proprietary drivers that have been
know to break in the past.

The first iteration of Libre-SOC targets a single-core at 180nm. Subsequent
generations target SMP cores at a smaller node size, for typical use in SBC
designs.

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[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=288

--- Comment #7 from Yehowshua <yimmanuel3@gatech.edu> ---
Sounds solid.

small typo on my part:

> that have been know to break in the past.

should be ``known"

Final revision?:
Libre-SOC is a Libre Hardware-Software project that aims to deliver a physical 
POWER compliant SOC that comes complete with a CPU, GPU, VPU, and DDR
controller. All the software and hardware from the drivers down to the RTL and
VLSI cells are libre-licensed. Libre-SOC is also providing the necessary
drivers amongst which include Kazan (a Vulkan 3D driver) and the full
bootloader and on-board boot firmware source.

The intended market includes customers who desire acceleration in the embedded
space without relying on ARM or 3rd party proprietary drivers that have been
known to break in the past.

The first iteration of Libre-SOC targets a single-core at 180nm. Subsequent
generations target SMP cores at a smaller node size, for typical use in SBC
designs.

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[libre-riscv-dev] [Bug 288] intro post for powerpc-notebook.org and https://www.powerprogress.org/en/

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=288

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)

> full bootloader and on-board boot firmware source.

on-board boot ROM, sorry.  shorter.  if everyone's good with it
i'll write to roberto.

next we need to work out what (and where) to put something
about these:
https://www.powerprogress.org/en/
https://www.powerpc-notebook.org/en/

this is a good clean design, i like it
https://i0.wp.com/www.powerpc-notebook.org/wp-content/uploads/2020/04/ppc_bloc_diagram_05_04_2020_s.png?ssl=1

it's actually pretty similar to what would go on our SoCs,
particularly if we could get hold of a PCIe PHY.

however... 2x DDR3, that's 250-300 pins, right there.
(actually just found the datasheet, it's 1x 32/64 so will
be around... 200-250).  3 PCIE x4
plus a PCIe x2, is... a looot more.  300+ i think.

datasheet says it's 780 pins FP-PBGA, 23x23mm

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