[libre-riscv-dev] [Bug 316] bperm TODO

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=316

--- Comment #93 from Cole Poirier <colepoirier@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #92)
> Big endianess: LSB starts at top numbered wire, MSB is in wire 0.
> 
> little: LSB is in wire 0.
> 
> to access 64 bit in BE you do this
> x[63-index]
> not
> x[index]
> 
> to access 32 bit in BE you do this:
> x[31-index]
> 
> so somewhere, that is what is needed.

I think I've tried every possible combination at this point and I am still
unable to make progress. This is the current state of my bpermd.py module, that
at least doesn't just output 0 every time. I think I have tried all possible
permutations of 63-index and 7-index, but still cannot get it to produce
correct results. Can you please give me some guidance?

```
def elaborate(self, platform):
    m = Module()
    perm = Signal(self.width, reset_less=True)
    rb64 = [Signal(1, reset_less=True, name=f"rb64_{i}") for i in range(64)]
    for i in range(64):
        m.d.comb += rb64[i].eq(self.rb[63-i])
        rb64 = Array(rb64)
        for i in range(8):
            index = self.rs[8*(7-i)+8:8*(7-i):-1]
            idx = Signal(8, name=f"idx_{i}", reset_less=True)
            m.d.comb += idx.eq(index)
            with m.If(idx < 64):
                m.d.comb += perm[7-i].eq(rb64[63-idx])
    m.d.comb += self.ra[0:8].eq(perm)
    return m
```

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