[libre-riscv-dev] [Bug 316] bperm TODO

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=316

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Cole Poirier from comment #16)

> I have committed the changes.

fantastic: feel free to do another "git pull" because i just made some
PEP8-like
changes.

btw notice in cr/main_stage.py, michael also does the same "indexing" trick :)
in particular notice what he does with the name argument:

   cr_out_arr = Array([Signal(name=f"cr_out_{i}") for i in range(32)])

if you try that out you will end up with actual properly-named Signals rather
than "stuff that's randomly named $1, $2, $3.... $64".


> Now I am going to go over Robert Baruch's
> nmigen tutorials and search out resources on writing unit tests, and formal
> proofs for hardware. Then I will attempt to write an appropriate unit test
> for this class.

great.  formal proofs are... odd.  i can barely get my head round them.

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