[libre-riscv-dev] [Bug 316] bperm TODO

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=316

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Cole Poirier from comment #3)

>     m.d.comb += self.perm[i].eq(self.rb[index])
>   File "/home/colepoirier/src/nmigen/nmigen/hdl/ast.py", line 253, in
> __getitem__
>     raise TypeError("Cannot index value with {}".format(repr(key)))
> TypeError: Cannot index value with (slice (sig rs) 0:8)

err... err.... ah :)  rrrright, you need to use nmigen.Array.

basically:

* create a list of 64 signals, each 1-bit wide, for-loop, append them each to
the
  list
* assign 1 bit of rb into each of those 64 (signal_1_bit.eq(rb[i]) 
* create the array: rb8 = Array(my_list_of_64_signals)

*then* you can index them.

however... be aware that this is an absolutely truly dreadful way to do it :)
it will at least be functional and we can work on an improved design in a
second iteration.

basically it is absolutely awful because we are creating a *SIXTY FOUR* way
crossbar... actually 8 such 64-way crossbars!

this is pretty massive.

however... before completely freaking out, it is worthwhile seeing what
yosys actually generates (synth command).  it *might* actually generate
an efficient design.  we have to see.

if it really doesn't, then we can look around for alternatives.  there might
be something in clifford wolf's excellent bitmanip code.

but - go through with this as it is, then write a unit test.  you will then
have "something to test an alternative design against", later.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev