[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=348

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
OP_MFSPR - note that XER is "constructed"

report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
    "=" & to_hstring(a_in);
if is_fast_spr(e_in.read_reg1) then
    result := a_in;
    if decode_spr_num(e_in.insn) = SPR_XER then
        -- bits 0:31 and 35:43 are treated as reserved and return 0s
        -- when read using mfxer
        result(63 downto 32) := (others => '0');
        result(63-32) := v.e.xerc.so;
        result(63-33) := v.e.xerc.ov;
        result(63-34) := v.e.xerc.ca;
        result(63-35 downto 63-43) := "000000000";
        result(63-44) := v.e.xerc.ov32;
        result(63-45) := v.e.xerc.ca32;
else
    case decode_spr_num(e_in.insn) is
    when SPR_TB =>              result := ctrl.tb;
    when SPR_DEC =>             result := ctrl.dec;
    when others =>              result := (others => '0');
    end case;

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