[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=348

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
OP_MTSPR:

if is_fast_spr(e_in.write_reg) then
    result := c_in;
    result_en := '1';
    if decode_spr_num(e_in.insn) = SPR_XER then
        v.e.xerc.so := c_in(63-32);
        v.e.xerc.ov := c_in(63-33);
        v.e.xerc.ca := c_in(63-34);
        v.e.xerc.ov32 := c_in(63-44);
        v.e.xerc.ca32 := c_in(63-45);
        v.e.write_xerc_enable := '1';
else
    -- slow spr
    case decode_spr_num(e_in.insn) is
    when SPR_DEC =>
        ctrl_tmp.dec <= c_in;
    when others =>
        -- mtspr to unimplemented SPRs should be a nop in
        -- supervisor mode and a program interrupt for user mode
        if ctrl.msr(MSR_PR) = '1' then
              illegal := '1';
    end case;

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