[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=348

--- Comment #5 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> (In reply to Jacob Lifshay from comment #3)
> > (In reply to Luke Kenneth Casson Leighton from comment #1)
> > >     if decode_spr_num(e_in.insn) = SPR_XER then
> > > 	-- bits 0:31 and 35:43 are treated as reserved and return 0s
> > >         -- when read using mfxer
> > 
> > from what I recall, at least some of the reserved XER bits are software
> > writable and need to be implemented.
> 
> can you recall where and drop the relevant text and ref here?  technically
> it is possible to shadow the bits from the slow SPR regfile but it is messy.

it's in section
3.2.2 Fixed-Point Exception Register page 50 (74 of PDF)
of Power ISA v3.1
<describing XER bit fields>
46:56 Reserved
Bits 48:55 are implemented, and can be read
and written by software as if the bits contained
a defined field.
57:63 This field specifies the number of bytes to be
transferred by a Load String Indexed or Store
String Indexed instruction.

Bits 48:55 of the XER correspond to bits 16:23 of
the XER in the POWER Architecture. In the
POWER Architecture bits 16:23 of the XER contain
the comparison byte for the lscbx instruction.
Power ISA lacks the lscbx instruction, but some
application programs that run on processors that
implement Power ISA may still use lscbx, and
privileged software may emulate the instruction.
XER48:55 may be assigned a meaning in a future
version of the architecture, when POWER compati-
bility for lscbx is no longer needed, so these bits
should not be used for purposes other than the
lscbx comparison byte.

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