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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 348] New: POWER9 SPR pipeline needed
Date: Sun, 24 May 2020 21:46:58 +0000
Message-ID: <bug-348-13@https.bugs.libre-soc.org/> (raw)

https://bugs.libre-soc.org/show_bug.cgi?id=348

            Bug ID: 348
           Summary: POWER9 SPR pipeline needed
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

OP_MTSPR, OP_MFSPR operations to be added to an SPR pipeline.
with some of the SPRs being in a separate regfile (XER, LR, CTR, SRR1, SRR2)
this pipeline is slightly more involved than it seems.   it also requires
quite a lot of regfile ports.

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Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-24 21:46 bugzilla-daemon [this message]
2020-05-24 21:49 ` [libre-riscv-dev] [Bug 348] " bugzilla-daemon
2020-05-27 14:57 ` bugzilla-daemon
2020-05-27 17:40 ` bugzilla-daemon
2020-05-27 17:58 ` bugzilla-daemon
2020-05-28 16:20 ` bugzilla-daemon
2020-06-05  4:02 ` bugzilla-daemon

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