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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
Date: Wed, 27 May 2020 17:58:34 +0000
Message-ID: <bug-348-13-ykSLMsoQC6@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-348-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=348

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)
> (In reply to Luke Kenneth Casson Leighton from comment #1)
> >     if decode_spr_num(e_in.insn) = SPR_XER then
> > 	-- bits 0:31 and 35:43 are treated as reserved and return 0s
> >         -- when read using mfxer
> 
> from what I recall, at least some of the reserved XER bits are software
> writable and need to be implemented.

can you recall where and drop the relevant text and ref here?  technically it
is possible to shadow the bits from the slow SPR regfile but it is messy.

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  parent reply index

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-24 21:46 [libre-riscv-dev] [Bug 348] New: " bugzilla-daemon
2020-05-24 21:49 ` [libre-riscv-dev] [Bug 348] " bugzilla-daemon
2020-05-27 14:57 ` bugzilla-daemon
2020-05-27 17:40 ` bugzilla-daemon
2020-05-27 17:58 ` bugzilla-daemon [this message]
2020-05-28 16:20 ` bugzilla-daemon
2020-06-05  4:02 ` bugzilla-daemon

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