[libre-riscv-dev] [Bug 348] New: POWER9 SPR pipeline needed

[libre-riscv-dev] [Bug 348] New: POWER9 SPR pipeline needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=348

            Bug ID: 348
           Summary: POWER9 SPR pipeline needed
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

OP_MTSPR, OP_MFSPR operations to be added to an SPR pipeline.
with some of the SPRs being in a separate regfile (XER, LR, CTR, SRR1, SRR2)
this pipeline is slightly more involved than it seems.   it also requires
quite a lot of regfile ports.

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[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=348

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
OP_MFSPR - note that XER is "constructed"

report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
    "=" & to_hstring(a_in);
if is_fast_spr(e_in.read_reg1) then
    result := a_in;
    if decode_spr_num(e_in.insn) = SPR_XER then
        -- bits 0:31 and 35:43 are treated as reserved and return 0s
        -- when read using mfxer
        result(63 downto 32) := (others => '0');
        result(63-32) := v.e.xerc.so;
        result(63-33) := v.e.xerc.ov;
        result(63-34) := v.e.xerc.ca;
        result(63-35 downto 63-43) := "000000000";
        result(63-44) := v.e.xerc.ov32;
        result(63-45) := v.e.xerc.ca32;
else
    case decode_spr_num(e_in.insn) is
    when SPR_TB =>              result := ctrl.tb;
    when SPR_DEC =>             result := ctrl.dec;
    when others =>              result := (others => '0');
    end case;

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[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=348

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
OP_MTSPR:

if is_fast_spr(e_in.write_reg) then
    result := c_in;
    result_en := '1';
    if decode_spr_num(e_in.insn) = SPR_XER then
        v.e.xerc.so := c_in(63-32);
        v.e.xerc.ov := c_in(63-33);
        v.e.xerc.ca := c_in(63-34);
        v.e.xerc.ov32 := c_in(63-44);
        v.e.xerc.ca32 := c_in(63-45);
        v.e.write_xerc_enable := '1';
else
    -- slow spr
    case decode_spr_num(e_in.insn) is
    when SPR_DEC =>
        ctrl_tmp.dec <= c_in;
    when others =>
        -- mtspr to unimplemented SPRs should be a nop in
        -- supervisor mode and a program interrupt for user mode
        if ctrl.msr(MSR_PR) = '1' then
              illegal := '1';
    end case;

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[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=348

Jacob Lifshay <programmerjake@gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |programmerjake@gmail.com

--- Comment #3 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
>     if decode_spr_num(e_in.insn) = SPR_XER then
> 	-- bits 0:31 and 35:43 are treated as reserved and return 0s
>         -- when read using mfxer

from what I recall, at least some of the reserved XER bits are software
writable and need to be implemented.

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[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=348

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)
> (In reply to Luke Kenneth Casson Leighton from comment #1)
> >     if decode_spr_num(e_in.insn) = SPR_XER then
> > 	-- bits 0:31 and 35:43 are treated as reserved and return 0s
> >         -- when read using mfxer
> 
> from what I recall, at least some of the reserved XER bits are software
> writable and need to be implemented.

can you recall where and drop the relevant text and ref here?  technically it
is possible to shadow the bits from the slow SPR regfile but it is messy.

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[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=348

--- Comment #5 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> (In reply to Jacob Lifshay from comment #3)
> > (In reply to Luke Kenneth Casson Leighton from comment #1)
> > >     if decode_spr_num(e_in.insn) = SPR_XER then
> > > 	-- bits 0:31 and 35:43 are treated as reserved and return 0s
> > >         -- when read using mfxer
> > 
> > from what I recall, at least some of the reserved XER bits are software
> > writable and need to be implemented.
> 
> can you recall where and drop the relevant text and ref here?  technically
> it is possible to shadow the bits from the slow SPR regfile but it is messy.

it's in section
3.2.2 Fixed-Point Exception Register page 50 (74 of PDF)
of Power ISA v3.1
<describing XER bit fields>
46:56 Reserved
Bits 48:55 are implemented, and can be read
and written by software as if the bits contained
a defined field.
57:63 This field specifies the number of bytes to be
transferred by a Load String Indexed or Store
String Indexed instruction.

Bits 48:55 of the XER correspond to bits 16:23 of
the XER in the POWER Architecture. In the
POWER Architecture bits 16:23 of the XER contain
the comparison byte for the lscbx instruction.
Power ISA lacks the lscbx instruction, but some
application programs that run on processors that
implement Power ISA may still use lscbx, and
privileged software may emulate the instruction.
XER48:55 may be assigned a meaning in a future
version of the architecture, when POWER compati-
bility for lscbx is no longer needed, so these bits
should not be used for purposes other than the
lscbx comparison byte.

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[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=348

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
TODO: MFSPR/MTSPR need fast-reg decoding in PowerDecoder2 DecodeA and DecodeOut

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