[libre-riscv-dev] [Bug 350] New: LDSTCompUnit also needs to support zeroing on RA

[libre-riscv-dev] [Bug 350] New: LDSTCompUnit also needs to support zeroing on RA

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=350

            Bug ID: 350
           Summary: LDSTCompUnit also needs to support zeroing on RA
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

https://libre-soc.org/openpower/isa/fixedload/

noted that zeroing on RA is possible

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[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=350

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=318

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[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=350

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=336
    NLnet milestone|---                         |NLnet.2019.02

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[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=350

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
added, untested, however may have a block when both zero and immediate set.

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[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=350

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> added, untested, however may have a block when both zero and immediate set.

it's fine.  unit test modified as follows:

+    rd = 0b00
+    if not imm_ok:
+        rd |= 0b10
+    if not zero_a:
+        rd |= 0b01
+
+    if rd:
+        yield dut.rd.go.eq(rd)
+        yield from wait_for(dut.rd.rel)
+        yield dut.rd.go.eq(0)

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[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=350

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|lkcl@lkcl.net               |cestrauss@gmail.com

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
cesar this one likewise needs similar tests to the MultiCompUnit, might even
be able to share the same base classes at some point.

again it needs that "multi-process" simulation model:

* one function doing setup, setting oper_i, issue_i, then monitoring busy_o
  before exiting

* another that checks busy_o and, when set, proceeds to monitor a single
  bit of rd.req, sets the corresponding bit of rd.go for one cycle, then
  monitors busy_o before exiting

* likewise for write requests.

this is exactly the same as needed for MultiCompUnit (up to this point).
the additions obviously are to have extra functions that:

* monitor req_adr_o and set go_adr_i
* monitor req_st_o and set go_st_i
* check the address and the data afterwards

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[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=350

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=356

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