From: Lauri Kasanen <cand@gmx.com>
To: libre-riscv-dev@lists.libre-riscv.org
Subject: Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Date: Tue, 12 May 2020 09:01:44 +0300
Message-ID: <20200512090144.8fe5608fc7b63c8b6b33367a@gmx.com> (raw)
In-Reply-To: <20200511203421.5d834abb14dbc2b7c979c6f7@gmx.com>
Hi,
The thing that stood out to me in the levels was BE/LE. An int or float
compatible Power processor must support BE, LE is optional at those
levels. A Linux level processor must support LE, BE is optional at that
level. However the Linux level requires SIMD.
So this means that our int+float processor must support BE.
- Lauri
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Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 17:34 Lauri Kasanen
2020-05-11 18:25 ` Luke Kenneth Casson Leighton
2020-05-11 18:28 ` Luke Kenneth Casson Leighton
2020-05-11 18:31 ` Yehowshua
2020-05-11 18:37 ` Luke Kenneth Casson Leighton
2020-05-12 6:01 ` Lauri Kasanen [this message]
2020-05-12 6:27 ` Jacob Lifshay
2020-05-12 6:44 ` Lauri Kasanen
2020-05-12 7:06 ` Jacob Lifshay
2020-05-12 7:56 ` Luke Kenneth Casson Leighton
2020-05-12 13:55 ` Hendrik Boom
2020-05-12 14:46 ` Luke Kenneth Casson Leighton
2020-05-12 15:11 ` Hendrik Boom
2020-05-12 15:56 ` Luke Kenneth Casson Leighton
2020-05-12 7:36 ` Luke Kenneth Casson Leighton
2020-05-12 7:50 ` Luke Kenneth Casson Leighton
2020-05-12 8:23 ` Lauri Kasanen
2020-05-12 8:33 ` Luke Kenneth Casson Leighton
2020-05-12 8:50 ` Lauri Kasanen
2020-05-12 9:09 ` Luke Kenneth Casson Leighton
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