From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Date: Tue, 12 May 2020 08:50:09 +0100
Message-ID: <CAPweEDw4siZsTwHd136CB8xZuiNeoA1X80fgdAv9NVj1N-nB=w@mail.gmail.com> (raw)
In-Reply-To: <20200512090144.8fe5608fc7b63c8b6b33367a@gmx.com>
On Tue, May 12, 2020 at 7:00 AM Lauri Kasanen <cand@gmx.com> wrote:
> level. However the Linux level requires SIMD.
this is more serious. the implementation burden of POWER SIMD
compliance is absolutely massive. a quick count from figure 91 i
estimate 600 instructions dedicated to INT and FP SIMD.
the scalar instruction set is much more manageable: there's 378
opcodes from microwatt CSV files, then there's 20 FP LD/ST, and
estimated 70 or so FP arithmetic and 8 or so status registers.
l.
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Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 17:34 Lauri Kasanen
2020-05-11 18:25 ` Luke Kenneth Casson Leighton
2020-05-11 18:28 ` Luke Kenneth Casson Leighton
2020-05-11 18:31 ` Yehowshua
2020-05-11 18:37 ` Luke Kenneth Casson Leighton
2020-05-12 6:01 ` Lauri Kasanen
2020-05-12 6:27 ` Jacob Lifshay
2020-05-12 6:44 ` Lauri Kasanen
2020-05-12 7:06 ` Jacob Lifshay
2020-05-12 7:56 ` Luke Kenneth Casson Leighton
2020-05-12 13:55 ` Hendrik Boom
2020-05-12 14:46 ` Luke Kenneth Casson Leighton
2020-05-12 15:11 ` Hendrik Boom
2020-05-12 15:56 ` Luke Kenneth Casson Leighton
2020-05-12 7:36 ` Luke Kenneth Casson Leighton
2020-05-12 7:50 ` Luke Kenneth Casson Leighton [this message]
2020-05-12 8:23 ` Lauri Kasanen
2020-05-12 8:33 ` Luke Kenneth Casson Leighton
2020-05-12 8:50 ` Lauri Kasanen
2020-05-12 9:09 ` Luke Kenneth Casson Leighton
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