From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Date: Tue, 12 May 2020 08:36:13 +0100
Message-ID: <CAPweEDyicNtwDM_a4_1cztAuHidBb44m-N3S8ij0eC6shd=nNA@mail.gmail.com> (raw)
In-Reply-To: <20200512090144.8fe5608fc7b63c8b6b33367a@gmx.com>
On Tue, May 12, 2020 at 7:00 AM Lauri Kasanen <cand@gmx.com> wrote:
>
> Hi,
>
> The thing that stood out to me in the levels was BE/LE. An int or float
> compatible Power processor must support BE, LE is optional at those
> levels. A Linux level processor must support LE, BE is optional at that
> level. However the Linux level requires SIMD.
>
> So this means that our int+float processor must support BE.
michael and i have added BE byte-flipping into the instruction decode,
which is code used by both the simulator and the hardware.
we need BE because without it we cannot detect Compressed, VBLOCK or
SVPrefix modes in the same instruction stream as 32-bit operations,
because only in BE mode will the opcode be in the front 2 bytes in the
sequential bytes read from the instruction stream.
see https://libre-soc.org/openpower/
where it is mentioned that we will need to take 8 major opcodes to do
this: 2 bits per "mode".
l.
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Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 17:34 Lauri Kasanen
2020-05-11 18:25 ` Luke Kenneth Casson Leighton
2020-05-11 18:28 ` Luke Kenneth Casson Leighton
2020-05-11 18:31 ` Yehowshua
2020-05-11 18:37 ` Luke Kenneth Casson Leighton
2020-05-12 6:01 ` Lauri Kasanen
2020-05-12 6:27 ` Jacob Lifshay
2020-05-12 6:44 ` Lauri Kasanen
2020-05-12 7:06 ` Jacob Lifshay
2020-05-12 7:56 ` Luke Kenneth Casson Leighton
2020-05-12 13:55 ` Hendrik Boom
2020-05-12 14:46 ` Luke Kenneth Casson Leighton
2020-05-12 15:11 ` Hendrik Boom
2020-05-12 15:56 ` Luke Kenneth Casson Leighton
2020-05-12 7:36 ` Luke Kenneth Casson Leighton [this message]
2020-05-12 7:50 ` Luke Kenneth Casson Leighton
2020-05-12 8:23 ` Lauri Kasanen
2020-05-12 8:33 ` Luke Kenneth Casson Leighton
2020-05-12 8:50 ` Lauri Kasanen
2020-05-12 9:09 ` Luke Kenneth Casson Leighton
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