From: Lauri Kasanen <cand@gmx.com>
To: libre-riscv-dev@lists.libre-riscv.org
Subject: Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Date: Tue, 12 May 2020 11:50:42 +0300
Message-ID: <20200512115042.484e26aeb757d9473b885979@gmx.com> (raw)
In-Reply-To: <CAPweEDxqj+YZZyKXHL+=9uhGpRb5GEZeHtQw-Z=mx=_6ZCN3Sg@mail.gmail.com>
On Tue, 12 May 2020 09:33:52 +0100
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> i recall (and could be wrong about) seeing that there's different
> bits, one covering instructions, one covering data. would need to
> read them more closely. are you saying that the BE-for-instructions
> bit will flip *data* order as well?
I'm not that familiar with the low level details, I was speaking from
the compliance POV. Aka BE instructions only is not enough to be
compliant. If there are plans to support full BE, then it'd be fine.
- Lauri
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Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 17:34 Lauri Kasanen
2020-05-11 18:25 ` Luke Kenneth Casson Leighton
2020-05-11 18:28 ` Luke Kenneth Casson Leighton
2020-05-11 18:31 ` Yehowshua
2020-05-11 18:37 ` Luke Kenneth Casson Leighton
2020-05-12 6:01 ` Lauri Kasanen
2020-05-12 6:27 ` Jacob Lifshay
2020-05-12 6:44 ` Lauri Kasanen
2020-05-12 7:06 ` Jacob Lifshay
2020-05-12 7:56 ` Luke Kenneth Casson Leighton
2020-05-12 13:55 ` Hendrik Boom
2020-05-12 14:46 ` Luke Kenneth Casson Leighton
2020-05-12 15:11 ` Hendrik Boom
2020-05-12 15:56 ` Luke Kenneth Casson Leighton
2020-05-12 7:36 ` Luke Kenneth Casson Leighton
2020-05-12 7:50 ` Luke Kenneth Casson Leighton
2020-05-12 8:23 ` Lauri Kasanen
2020-05-12 8:33 ` Luke Kenneth Casson Leighton
2020-05-12 8:50 ` Lauri Kasanen [this message]
2020-05-12 9:09 ` Luke Kenneth Casson Leighton
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