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From: Staf Verhaegen <staf@fibraservi.eu>
To: libre-riscv-dev@lists.libre-riscv.org
Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
Date: Fri, 08 May 2020 19:23:35 +0200
Message-ID: <63e8b9ce54648590e2a6fc51bc2110dde7585f5e.camel@fibraservi.eu> (raw)
In-Reply-To: <CAPweEDzdkhVJuJ3_UqZTbd7i7vXJ5iiu3qz+LUBsFRJrzCcEmQ@mail.gmail.com>

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Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 17:55 [+0100]:
> On Fri, May 8, 2020 at 4:27 PM <whygee@f-cpu.org> wrote:
> > To me JTAG/TAP/debug port shine from its absence.
> 
> yep good catch.  added.

I already have (alpha version) nmigen JTAG code: https://gitlab.com/Chips4Makers/c4m-jtagStaf. id="-x-evo-selection-start-marker">


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Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-08  9:50 [libre-riscv-dev] minimum viable ASIC Luke Kenneth Casson Leighton
2020-05-08 10:29 ` Staf Verhaegen
2020-05-08 10:42   ` Luke Kenneth Casson Leighton
2020-05-08 11:10     ` Staf Verhaegen
2020-05-08 12:43   ` Yehowshua
2020-05-08 12:46     ` Luke Kenneth Casson Leighton
2020-05-08 19:08       ` Staf Verhaegen
2020-05-08 20:35         ` Luke Kenneth Casson Leighton
2020-05-08 12:49 ` Yehowshua
2020-05-08 12:50   ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 12:59   ` Yehowshua
2020-05-08 14:59   ` Luke Kenneth Casson Leighton
2020-05-08 15:00     ` Yehowshua
2020-05-08 15:27 ` [libre-riscv-dev] Debug port (was Re: minimum viable ASIC) whygee
2020-05-08 16:55   ` Luke Kenneth Casson Leighton
2020-05-08 17:23     ` Staf Verhaegen [this message]
2020-05-08 22:19       ` Luke Kenneth Casson Leighton
2020-05-20 16:44         ` Staf Verhaegen
2020-05-20 17:22           ` Luke Kenneth Casson Leighton
2020-05-29 10:30             ` Luke Kenneth Casson Leighton

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