From: whygee@f-cpu.org
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
Date: Fri, 08 May 2020 17:27:06 +0200
Message-ID: <9191058ea0912f2b508a6f73ea567e5f@f-cpu.org> (raw)
In-Reply-To: <CAPweEDw862-S1=Au1YbsKNy0629pa56eShp+2o_Avd96Auz8mw@mail.gmail.com>
On 2020-05-08 11:50, Luke Kenneth Casson Leighton wrote:
> i'd like to discuss what the minimum viable ASIC would look like,
> that, if we're happy to do so, we could hit the October 2020 deadline
> with it and not be completely stressed.
>
<snip>
>
> thoughts appreciated.
To me JTAG/TAP/debug port shine from its absence.
how will you "talk" with the chip when it
arrives from factory and you want to ensure
all its pins are correctly soldered/bonded
and you want to explore the insides to
test each unit ?
> l.
yg
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Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 9:50 [libre-riscv-dev] minimum viable ASIC Luke Kenneth Casson Leighton
2020-05-08 10:29 ` Staf Verhaegen
2020-05-08 10:42 ` Luke Kenneth Casson Leighton
2020-05-08 11:10 ` Staf Verhaegen
2020-05-08 12:43 ` Yehowshua
2020-05-08 12:46 ` Luke Kenneth Casson Leighton
2020-05-08 19:08 ` Staf Verhaegen
2020-05-08 20:35 ` Luke Kenneth Casson Leighton
2020-05-08 12:49 ` Yehowshua
2020-05-08 12:50 ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 14:59 ` Luke Kenneth Casson Leighton
2020-05-08 15:00 ` Yehowshua
2020-05-08 15:27 ` whygee [this message]
2020-05-08 16:55 ` [libre-riscv-dev] Debug port (was Re: minimum viable ASIC) Luke Kenneth Casson Leighton
2020-05-08 17:23 ` Staf Verhaegen
2020-05-08 22:19 ` Luke Kenneth Casson Leighton
2020-05-20 16:44 ` Staf Verhaegen
2020-05-20 17:22 ` Luke Kenneth Casson Leighton
2020-05-29 10:30 ` Luke Kenneth Casson Leighton
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