From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] minimum viable ASIC
Date: Fri, 8 May 2020 13:46:49 +0100
Message-ID: <CAPweEDwCrPLonpnn6WapzLyeYkgCy9c7NoZM+HoVb6uaZ1J-Yw@mail.gmail.com> (raw)
In-Reply-To: <7E85F682-C471-4B1D-882A-8E7B54021E18@gatech.edu>
On Fri, May 8, 2020 at 1:44 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
> I talked to Raptor and if Series A doesn’t pan out in August, Raptor is willing to foot 30k for PLL design in exchange for some equity.
that's fantastic. it would give us (and any other team)
Foundry-independence. normally the PLL is available as a Standard
Cell from a Foundry... but only under NDA.
l.
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Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 9:50 Luke Kenneth Casson Leighton
2020-05-08 10:29 ` Staf Verhaegen
2020-05-08 10:42 ` Luke Kenneth Casson Leighton
2020-05-08 11:10 ` Staf Verhaegen
2020-05-08 12:43 ` Yehowshua
2020-05-08 12:46 ` Luke Kenneth Casson Leighton [this message]
2020-05-08 19:08 ` Staf Verhaegen
2020-05-08 20:35 ` Luke Kenneth Casson Leighton
2020-05-08 12:49 ` Yehowshua
2020-05-08 12:50 ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 14:59 ` Luke Kenneth Casson Leighton
2020-05-08 15:00 ` Yehowshua
2020-05-08 15:27 ` [libre-riscv-dev] Debug port (was Re: minimum viable ASIC) whygee
2020-05-08 16:55 ` Luke Kenneth Casson Leighton
2020-05-08 17:23 ` Staf Verhaegen
2020-05-08 22:19 ` Luke Kenneth Casson Leighton
2020-05-20 16:44 ` Staf Verhaegen
2020-05-20 17:22 ` Luke Kenneth Casson Leighton
2020-05-29 10:30 ` Luke Kenneth Casson Leighton
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