From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
Date: Fri, 29 May 2020 11:30:49 +0100
Message-ID: <CAPweEDxF8_iZUgSCxJqXiQfHGDEuHjRw=5uEC5EgmwhrPsaXjg@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDxRMyVdga44mJ6GL+jOHxAz=DrwqFJEB013Eh3rVqCb6A@mail.gmail.com>
On Wednesday, May 20, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
import nmigen as nm
> x = nm.Signal()
>
> is actually a really good idea. saves space, explicitly says where
> the "thing" (Signal etc.) come from.
i found some code where we do just module import:
https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/singlepipe.py;h=cbd06f648b23a3ad6e9b064093de0f039c76bb32;hb=HEAD#l877
similar to "import operator" or "import math" then use
math.pi
math.cos(x)
operator.add
etc.
this is very good practice, Staf, because it allows the reader, at the
point of use of the function or class, to know immediately without
scrolling to the top of the page, which module the code comes from.
whilst *you* might know that, other readers will not. the additional
context is critical for *their* understanding and to not force them to work
harder, slowing them down to the point where mistakes are made or they give
up and find someone else's code.
bottom line: it's not about you :) these are practices that make life
easier for *other people*.
l.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 9:50 [libre-riscv-dev] minimum viable ASIC Luke Kenneth Casson Leighton
2020-05-08 10:29 ` Staf Verhaegen
2020-05-08 10:42 ` Luke Kenneth Casson Leighton
2020-05-08 11:10 ` Staf Verhaegen
2020-05-08 12:43 ` Yehowshua
2020-05-08 12:46 ` Luke Kenneth Casson Leighton
2020-05-08 19:08 ` Staf Verhaegen
2020-05-08 20:35 ` Luke Kenneth Casson Leighton
2020-05-08 12:49 ` Yehowshua
2020-05-08 12:50 ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 14:59 ` Luke Kenneth Casson Leighton
2020-05-08 15:00 ` Yehowshua
2020-05-08 15:27 ` [libre-riscv-dev] Debug port (was Re: minimum viable ASIC) whygee
2020-05-08 16:55 ` Luke Kenneth Casson Leighton
2020-05-08 17:23 ` Staf Verhaegen
2020-05-08 22:19 ` Luke Kenneth Casson Leighton
2020-05-20 16:44 ` Staf Verhaegen
2020-05-20 17:22 ` Luke Kenneth Casson Leighton
2020-05-29 10:30 ` Luke Kenneth Casson Leighton [this message]
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