From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] minimum viable ASIC
Date: Fri, 8 May 2020 08:50:12 -0400
Message-ID: <F8879D72-C787-4F35-BBC3-DF3E376344A5@gatech.edu> (raw)
In-Reply-To: <D725A5C8-7A3C-4403-9BF2-CA73B76CA7F5@gatech.edu>
But really guys, I’m betting the Series A will be just fine, from it, we can hire some talented engineers, and from then on, execution, not finances will be our bottleneck.
What I really need is an “hello world” on FPGA by demo day for August.
Yehowshua
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Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 9:50 Luke Kenneth Casson Leighton
2020-05-08 10:29 ` Staf Verhaegen
2020-05-08 10:42 ` Luke Kenneth Casson Leighton
2020-05-08 11:10 ` Staf Verhaegen
2020-05-08 12:43 ` Yehowshua
2020-05-08 12:46 ` Luke Kenneth Casson Leighton
2020-05-08 19:08 ` Staf Verhaegen
2020-05-08 20:35 ` Luke Kenneth Casson Leighton
2020-05-08 12:49 ` Yehowshua
2020-05-08 12:50 ` Yehowshua [this message]
2020-05-08 12:59 ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 14:59 ` Luke Kenneth Casson Leighton
2020-05-08 15:00 ` Yehowshua
2020-05-08 15:27 ` [libre-riscv-dev] Debug port (was Re: minimum viable ASIC) whygee
2020-05-08 16:55 ` Luke Kenneth Casson Leighton
2020-05-08 17:23 ` Staf Verhaegen
2020-05-08 22:19 ` Luke Kenneth Casson Leighton
2020-05-20 16:44 ` Staf Verhaegen
2020-05-20 17:22 ` Luke Kenneth Casson Leighton
2020-05-29 10:30 ` Luke Kenneth Casson Leighton
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